Power Management Logic Research Articles

Usage-Driven Personalization of Power Management Logic

The design of the power management logic (PML) of complex low-power system-on-chip (SoC) designs is rooted in the expected workload patterns in the target architecture. The increasing functionality of SoCs is complimented by increasingly diverse usage patterns among its users, leading to a situation where the same device is power efficient for some user and power inefficient for others. This letter positions the potential benefits of personalizing the PML in SoCs leveraging that the global power management strategy resides in firmware.

Assertions for Protecting Mixed-Signal Latency Contracts in Power Management

Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consider the real time latencies of the analog components, which otherwise leads to functional errors in the domains being driven. The latencies may be viewed as contracts between the digital and the analog. This article presents an approach for generating assertions for protecting such mixed-signal latency contracts and using them to rule out timing bugs in the power management logic. Our tool flow enables the verification of the power management fabric, combining a novel mixed-signal assertion checking method in a simulation setting, and a full formal verification method for the digital brain of the power management logic. To the best of our knowledge, this is the first framework where assertions are used for binding analog latency contracts on the digital logic of power management.

Formal Hardware/Software Co-Verification of Embedded Power Controllers

This paper reports for the first time, the use of a hardware-software combined bounded model checking approach for hardware-software mixed implementations of power management logic. We report significant performance gains as compared to our earlier attempt of extracting a finite quotient transition system from the control software.

Formal Verification of Architectural Power Intent

This paper presents a verification framework that attempts to bridge the disconnect between high-level properties capturing the architectural power management strategy and the implementation of the power management control logic using low-level per-domain control signals. The novelty of the proposed framework is in demonstrating that the architectural power intent properties developed using high-level artifacts can be automatically translated into properties over low-level control sequences gleaned from UPF specifications of power domains, and that the resulting properties can be used to formally verify the global on-chip power management logic. The proposed translation uses a considerable amount of domain knowledge and is also not purely syntactic, because it requires formal extraction of timing information for the low-level control sequences. We present a tool, called POWER-TRUCTOR which enables the proposed framework, and several test cases of significant complexity to demonstrate the feasibility of the proposed framework.

Cell Processor Low-Power Design Methodology

Power consumption is a major challenge in VLSI design. Power-constrained designs must attack power reduction with many techniques and require tools to accurately predict the power consumption. These tools give designers feedback on the efficiency of the power management logic. We present the basic methodology behind cycle-accurate power estimation. This forms a basis for explaining the techniques used to reduce power in the first-generation Cell processor, along with data that correlates our hardware measurements against power estimates.