Power Management IC Research Articles

87‐2: Modeling and Simulation for Mitigating Display Noise Caused by PMIC Ripple

The output ripple of the Power Management IC (PMIC) is one of the causes of display panel noise. This paper introduces modeling and simulation methods aimed at predicting and mitigating noise induced by PMIC ripple. If the display panel simulation is performed using an ideal voltage source, the ripple characteristics of the PMIC cannot be included. The improved method accurately predicted the ripple of the voltage input to the panel by modeling flicker noise and thermal noise, which are the main causes of PMIC noise, and modeling the Z‐parameter and decoupling capacitor of the PCB. In addition, it was possible to minimize ripples and finally reduce display noise by optimizing the design of the power supply circuit.

Ferroelectric Domain Wall Delayer and Low-Dropout Regulator.

A switching-type power converter providing an accurate and stable switching output voltage against line/load variations and power supply ripple is mostly complicated in system-on-chip power management integrated circuits (PMICs) within a limited occupation area. Here we fabricated domain wall (DW) nanodevices using an X-cut LiNbO3 thin film on silicon. The domain switching event occurs after a delay time predicted by Merz's law under the applied voltage. But the output current is irrespective of the applied voltage and can be adjusted by conducting wall width as well as input resistance in the circuit. The regulating currents appear repetitively across the volatile interfacial domains between the nanodevice and electrode under intermittently applied voltages. A wall-current-limited domain switching model is developed to explain the phenomenon. The multifunctional DW nanodevices with smaller occupation areas can serve as compact low-dropout regulators in PMICs, time-domain delayers in energy-efficient neural network systems, and on-chip electrostatic discharge protection besides nonvolatile memories and selectors.

A Low Noise Neural Recording Frontend IC With Power Management for Closed-Loop Brain-Machine Interface Application.

Brain-machine Interface (BMI) with implantable bioelectronics systems can provide an alternative way to cure neural diseases, while a power management system plays an important role in providing a stable voltage supply for the implanted chip. a prototype system of power management integrated circuit (PMIC) with heavy load capability supplying artifacts tolerable neural recording integrated circuit (ATNR-IC) is presented in this work. A reverse nested miller compensation (RNMC) low dropout regulator (LDO) with a transient enhancer is proposed for the PMIC. The power consumption is 0.55 mW and 22.5 mW at standby (SB) and full stimulation (ST) load, respectively. For a full load transition, the overshoot and downshoot of the LDO are 110 mV and 71 mV, respectively, which help improve the load transient response during neural stimulation. With the load current peak-to-peak range is about 560 μA supplied by a 4-channel stimulator, the whole PMIC can output a stable 3.3 V supply voltage, which indicates that this PMIC can be extended for more stimulating channels' scenarios. When the ATNR-IC is supplied for presented PMIC through a voltage divider network, it can amplify the signal consisting of 1 mVpp simulated neural signal and 20 mVpp simulated artifact by 28 dB with no saturation.

A High Conversion Ratio DC–DC Boost Converter with Continuous Output Current Using Dual-Current Flows

Recently, the demand for small, low-cost electronics has increased the use of cost-effective tiny inductors in power-management ICs (PMICs). However, the conduction loss caused by the parasitic DC resistance (RDCR) of a small inductor leads to low efficiency, which reduces the battery usage time and may also cause thermal problems in mobile devices. In particular, these issues become critical when a conventional boost converter (CBC) is used to achieve high-output voltage due to the large inductor current. In addition, as the output voltage increases, a number of issues become more serious, such as large output voltage ripple, conversion-ratio limit, and overlap loss. To solve these issues, this paper proposed a high-voltage boost converter with dual-current flows (HVDF). The proposed HVDF can achieve a higher efficiency than a CBC by reducing the total conduction loss in heavy load current conditions with a small inductor. Moreover, because in the HVDF, the current delivered to the output becomes continuous, unlike in the CBC with its discontinuous output delivery current, the output voltage ripple can be significantly reduced. Also, the conversion gain of the HVDF is less sensitive to RDCR than that of the CBC. To further increase the conversion gain, a time-interleaved charge pump can be connected in series with the HVDF (HVDFCP) to achieve higher output voltage beyond the limit of the conversion gain in the HVDF while maintaining the advantages of a low inductor current and small output voltage ripple. Simulations using PSIM were performed along with a detailed numerical analysis of the conduction losses in the proposed structures. The simulation results were discussed and compared with those of the conventional structures.

Triboelectric charge modulation to understand the electrification process in nanogenerators combined with an efficient power management system for IoT applications

Mechanical energy harvesting from ambient environment has been considered one of the promising technologies for developing autonomous self-powering units, sensors, and various other electronic applications. Triboelectric nanogenerators (TENGs) are one of the recent technologies gaining tremendous interest because of their ability to efficiently harvest ambient energy and convert it into electricity. The phenomenon of the triboelectrification effect in TENGs is not fully understood, along with extracting a maximum electrical output. Herein, we studied the electrification process between two triboelectric films by modulating their charge polarity. The charge polarity in the triboelectric film was modulated without any surface chemical functionalization. A TENG was fabricated to experimentally study the electrification process. Initially, the accepting/donating electrons of a triboelectric film were modulated using fluorine and oxygen atoms contained in polymers and operated against an oppositely charged triboelectric film. After optimizing the electrical output and conducting various stability investigations, the electrical output from the TENG was enhanced. Ultra-low power management integrated circuit (PMIC) implemented in a 180 nm high-voltage BCD (Bipolar CMOS DMOS) process was used. While matching the effective impedance of the TENGs, the PMIC achieves a total energy transfer efficiency of 81.5% utilizing a relatively low input power of 6.5 µW, showing state-of-the-art performance.

Analysis and Experiment of Self‐Powered, Pulse‐Based Energy Harvester Using 400 V FEP‐Based Segmented Triboelectric Nanogenerators and 98.2% Tracking Efficient Power Management IC for Multi‐Functional IoT Applications

AbstractA self‐powered system for the Internet of Things (IoT) is demonstrated for efficient energy harvesting of naturally available mechanical energy. In this system, new contact‐separation mode triboelectric nanogenerators (TENGs), based on fluorinated ethylene propylene, are investigated using the segmented multi‐TENG configuration to reduce the effect of parasitic capacitance. The TENG extraction is optimized using a unit step excitation involved with the Dawson function to achieve a high voltage (400 V) and a high current (26.6 µA). To fully extract the power of the TENGs, the power management integrated circuit (PMIC) specially designed for adaptively controlled, high‐voltage (HV) maximum power point tracking (MPPT) is proposed. The PMIC implemented in a bipolar CMOS‐DMOS 180 nm process can handle a wide input range (5–70 V) by consuming 420 nW. The MPPT control allows a wide range of impedance matching from 10 to 300 MΩ, achieving a tracking efficiency of up to 98.2%. The end‐to‐end efficiency of 88% demonstrates state‐of‐the‐art performance. To supply a higher instantaneous power than that available from the TENGs, a duty‐cycling technique is successfully demonstrated. The proposed energy harvesting system provides a promising approach to realizing sustainable and autonomous energy sources for various IoT applications.

Design and Implementation of Hybrid DC-DC Converter: A Review

The advancement in Power Management Integrated Circuit (PMIC) has driven the DC-DC conversion technology into a System-on-Chip (SoC) solutions, leveraging CMOS technology scaling from 180nm to 22nm and on-chip passive element integration. Concurrently, as the applications demand smaller form factor solution towards device portability with optimized power qualities, switched-capacitor-inductor hybrid architectures with fully-integrated passives have become a popular choice for a compact and high efficiency converter solution, in contrast to bulky and discrete component based alternatives. This article reviews the latest advancements in hybrid dc-dc topologies, specifically for low-power applications to address the downsides such as charge sharing loss, high current ripple, limited conversion ratio, low power density and efficiency. An overview of capacitor and inductor technology is discussed in terms of on-chip parasitic losses, and miniaturization. A comprehensive comparison in the state-of-the-art hybrid dc-dc converter work is tabulated with power density and efficiency as the primary performance metrics, highlighting their operability in low-power applications. Moreover, a discussion is included with quantified benchmarks to justify the viability of converters, along with the future recommendation of realizing ultra-high switching frequency for smaller footprint inductor and design approach to resolve the current tradeoff bottlenecks.

A Design of Wireless Power Receiver With Gate Charge Recycled Dual-Mode Active Rectifier and Step-Down Converter With 88.2% System Efficiency for Power Management IC

This article presents a power management integrated circuit for a wireless power receiver unit. A dual-mode high-efficiency active rectifier design is based on alliance for wireless power (A4WP) and wireless power consortium (WPC) standards. A gate charge recycling technique is proposed in the dual-mode active rectifier so that the current generated by the switching of the high side gate driver can be recycled to the rectifier output voltage in order to enhance efficiency. A step-down dc–dc converter with a proposed bootstrap circuit and dynamic pull-up resistor gate driver circuit is designed. The chip is implemented in a 0.18-μm bipolar-CMOS double-diffused metal-oxide-semiconductor process. The total die area, including the pad, is 2.64 mm × 2.6 mm. The measurement results show that the active rectifier achieves peak power conversion efficiency (PCE) of 94.7% and generates an output voltage of 7.68 V in WPC mode and 9.1 V with 93.4% efficiency in A4WPC mode. The input voltage varies from 10 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P-P</sub> –12 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P-P</sub> . Similarly, the step-down dc–dc converter obtains a peak PCE of 93.2% at a load current of 500 mA while producing an output voltage of 5 V. The overall system efficiency at A4WP and WPC mode are 86.7% and 88.2%, respectively.

Developing a TEI-Aware PMIC for Ultra-Low-Power System-on-Chips

As the demand for ultra-low-power (ULP) devices has increased tremendously, system-on-chip (SoC) designs based on ultra-low-voltage (ULV) operation have been receiving great attention. Moreover, research has shown the remarkable potential that even more power savings can be achieved in ULV SoCs by exploiting the temperature effect inversion (TEI) phenomenon, i.e., the delay of the ULV SoCs decreases with increasing temperature. However, TEI-aware low-power (TEI-LP) techniques have a critical limitation in practical terms, in that dedicated power management-integrated circuits (PMICs) have not yet been developed. In other words, it is essential to develop PMICs that automatically bring out the full potential of the TEI-LP techniques as the chip temperature changes. With the aim of designing such PMICs, this paper first conducted a study to find the most suitable DC-DC converter for PMICs and then developed a control algorithm to maximize the effectiveness of the TEI-LP techniques. Furthermore, we have developed a compact hardware controller for the algorithm to operate most energy efficiently on ULP-SoCs.

Seamless Capacitive Body Channel Wireless Power Transmission Toward Freely Moving Multiple Animals in an Animal Cage.

Unstable wireless power transmission toward multiple living animals in an animal cage is one of the significant barriers to performing long-term and real-time neural monitoring in preclinical research. Here, seamless capacitive body channel (SCB) wireless power transmission (WPT) along with power management integrated circuit (PMIC) is designed using a standard 65 nm CMOS process. The SCB WPT enables stable wireless power transmission toward multiple 35 mm×20 mm×2 mm sized receivers (RXs) attached to freely moving animals in a 600 mm×600 mm×120 mm sized animal cage. By utilizing fringe-field capacitance and a body channel for wireless power link between the cage and RXs, the maximum difference in all measured power efficiencies in diverse scenarios is only 6.66 % with a 20 mW load. Even with a 90 ° RX rotation against the cage, power efficiency marks 17.76 %. Furthermore, an in-vivo experiment conducted with three untethered rats demonstrates the capability of continuous long-term power delivery in practical situations.

A waterwheel hybrid generator with disk triboelectric nanogenerator and electromagnetic generator as a power source for an electrocoagulation system

Electrocoagulation (EC) method has emerged as a state-of-the-art water purifying technology. Here, a self-powered EC system is proposed using a waterwheel hybrid generator (W-HG) based on disk-type triboelectric nanogenerator (D-TENG) and electromagnetic generator (EMG). D-TENG consists of a rotator and stator based on printed circuit board (PCB) technology. With electrospinning and sintering process for polytetrafluoroethylene (PTFE) as a dielectric layer of the D-TENG, the fabricated membrane exhibits superhydrophobic property with a water contact angle of 160.5°, which allows the device to show self-cleaning property and to operate at high relative humidity. Additionally, a fractal-design based switched-capacitor-converter (FSCC) is utilized with the high-frequency and high-output based D-TENG to operate commercial electronic devices. The hybridized W-HG exhibits 1.75 mW of the average power at the matching load resistance of 400 Ω. An energy conversion efficiency of the device between rotational input energy and electrical output energy marks at 8.75%. The D-TENG and EMG are combined with a rotating waterwheel to demonstrate their ability to power an EC purification system. A power management integrated circuit (PMIC) is utilized with the D-TENG for high current input to the EC module. Finally, the W-HG successfully purifies wastewater with a high removal ratio above 95% for 18 h.

Wireless Power Transfer and Management for Medical Applications: Wireless power

Wireless power transfer (WPT) plays an important role in medical devices that require contactless energy transfer for either direct powering or recharging their small batteries. Miniaturizing medical devices and improving their WPT link robustness against different variations (e.g., distance, alignment, and load changes) also demands an efficient and adaptive power-management IC (PMIC) to convert the incoming ac power carrier into one or multiple usable dc voltage supplies. This article summarizes the key techniques for WPT and PMIC design. It discusses different modalities for WPT, including inductive, ultrasonic, capacitive, and magnetoelectric (ME) methods, with a focus on their applicability in different types of medical devices with different dimensions, implantation depths, and power requirements. It is concluded that ultrasonic and ME modalities are suitable for WPT to deeply implanted small devices with low power consumption, while inductive and capacitive methods are more suitable for WPT to large implants with shorter depth and higher power consumption. This article also summarizes different PMIC techniques for inductive WPT, particularly conventional voltage mode and more recent current-mode (and reconfigurable) techniques, with an emphasis on their suitability for different input voltage and loading conditions.

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review

Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.

Comparison of Dynamic Voltage Scaling (DVS) of Core Voltage Using the On-board Voltage Regulator and External Voltage Regulator via I2C Protocol in Automotive Micro controller

Dynamic Voltage Scaling is performed on automotive micro-controller AURIX from Infineon Technologies. In this micro-controller the core and different IPs operate on the 1.25 V supply rail, so dynamically voltage is changed according to the workload in the micro-controller. DVS is done either using an internal onboard voltage regulator or an external voltage regulator. An External board (KITPF3000FRDMEV), which has a controller and a Power Management Integrated Circuit (PMIC) is used for changing the supply voltage to the micro-controller during DVS using an external voltage regulator. The micro-controller is predicting the workload and according to workload, the control command is sent to the controller (FRDM-KL25) in the kit through I2C communication and then the controller sends the command to adjust the voltage of PMIC (PF3000) through I2C communication. Both current measurements for the internal voltage regulator and external voltage regulator are measured for various loads and latency is measured for various baud rates while using external voltage regulator through I2C protocol.

Tracking Automotive Electronics Related Sensory and Their Traceability by Boundary Scan Technology

This paper proposes several Python-based test methods to study a series of MCU-associated sensors. In light of today's automotive electronics, many electric systems are involved in modularized bare dies such as power management ICs along with embedded programming. As to the application of autonomous driving like the ADAS system, having many Multiple-Chips Modules (MCM) which are popular in SoC related functional boards. It is necessary to have these electrical systems follow stringent safety standards and regulations by the International Electrotechnical Commission (IEC). That is to ensure the electronic systems to be designed, implemented, operated within safety range. That is traceable according to the prerequisite Safety Integrity Level (SIL) besides the Automotive Safety Integrity Level (ASIL) towards five classes. These classes further evolved into higher requirements such as IEC-61508 and more recently the ISO-26262. All of these, have driven many companies to research and develop a suite of methods and strategies to solve some of the “reliability” associated issues, especially in the area of autonomous driving. This paper proposes the boundary scan based test methodology to cop with government’s regulations by tracking some of the major sensors in responses to motion, temperature and dynamic forces based on a JTAG’s sensor board in case study A. Thereafter, using an NXP’s automotive board to trace on board electronics, mainly the CPU and MCU via the MODBUS is made possible to log and record test results through VB.XML.NET. These languages speak uniformly to the relational data base in one “DataSet” by in-memory cache of the data retrieved from a database, in case study B. Both are realized by the JTAG’s Functional Test (JFT) system, to log the “pass or fail” results in a sequential execution. This paper illustrates how-to reach this goal through the process in use of the public-domain based open frame-ware, and to demonstrate them on a JTAG’s Provision platform throughout the development stages.

Energy Harvesting towards Self-Powered IoT Devices

The internet of things (IoT) manages a large infrastructure of web-enabled smart devices, small devices that use embedded systems, such as processors, sensors, and communication hardware to collect, send, and elaborate on data acquired from their environment. Thus, from a practical point of view, such devices are composed of power-efficient storage, scalable, and lightweight nodes needing power and batteries to operate. From the above reason, it appears clear that energy harvesting plays an important role in increasing the efficiency and lifetime of IoT devices. Moreover, from acquiring energy by the surrounding operational environment, energy harvesting is important to make the IoT device network more sustainable from the environmental point of view. Different state-of-the-art energy harvesters based on mechanical, aeroelastic, wind, solar, radiofrequency, and pyroelectric mechanisms are discussed in this review article. To reduce the power consumption of the batteries, a vital role is played by power management integrated circuits (PMICs), which help to enhance the system’s life span. Moreover, PMICs from different manufacturers that provide power management to IoT devices have been discussed in this paper. Furthermore, the energy harvesting networks can expose themselves to prominent security issues putting the secrecy of the system to risk. These possible attacks are also discussed in this review article.

Power Management IC With a Three-Phase Cold Self-Start for Thermoelectric Generators

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and 1080 μW output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV.

Analysis of Cascaded Multilevel Inverter with a Reduced Number of Switches for Reduction of Total Harmonic Distortion

Multilevel inverters (MLI) are aligned with lower harmonics and less commutation losses, which offer high power capacity. MLI is one of the best widespread converters due to its ability to eliminate the harmonic distortion without dropping the converter power output. The cascaded MLI is utilized for a reduced number of switches. In this topology, the switching angles at fundamental frequency are attained by solving the selective harmonic eliminations using sine cosine algorithm. This attains the desired output voltage with the elimination of certain lower order harmonics. In this paper, the analysis of seven-level cascaded MLI is presented with the scheme of carrier-based modulation techniques i.e. Phase-Disposition (PD), Phase-Opposition Disposition (POD) and Alternative Phase-Opposition Disposition (APOD). The Artificial intelligence (AI) is carried out for PD technique. These techniques are capable of defining the required switching angles to eliminate the preferred values of harmonics. The harmonic contents of output voltage in carrier-based modulation are observed with the indices, such as the modulation index with frequency modulation index and amplitude modulation index. The simulation results are obtained for seven-level inverter using MATLAB/SIMULINK. The hardware implementation is carried out using Main Power Management IC TPS65217C Beagle Bone Black Board for seven-level open loop control to justify the achievement of the suggested topology.

Switch Stacking in Power Management ICs

The stacking of low-voltage transistors brings several advantages for the design of power management integrated circuits (PMICs). Process nodes and, thereby, the I/O voltage of the core devices shrink down, while the supply voltages of many applications cannot be reduced at the same rate. The stacking of low-voltage devices is often more area- and energy-efficient compared with using one high-voltage transistor. This work proposes an implementation option for the stacking of three low-voltage transistors, which, as a significant advantage, does not require additional supply rails as required in the prior art. It is independent of the input voltage and can, therefore, be widely used in different PMIC designs. The overall article is set up in a survey and tutorial style. It gives an overview of existing solutions and presents best-practice design guidelines for proper implementation of up to four stacked switches. The efficiency benefit of low-voltage transistor stacking over single high-voltage switches is investigated with a model of the transistor stack. Experimental results for loss energy and area consumption of various switch configurations in 130-nm CMOS confirm the presented design aspects. The advantages are also demonstrated by measurement results of a hybrid dc-dc converter with optimized power switch stacking.

Triple-Mode Switched-Inductor-Capacitor DC-DC Buck Converter with Reusable Flying Capacitor and Bang-Bang Zero-Current Detector for Wide Load Current Range

Although the capacity of a battery with a small form factor is extremely low, demand for long usage time of Internet of Things (IoT) products is increasing. Owing to this limitation of the battery, power management integrated circuits (PMICs) are used for extending the battery usage time with high efficiency. In particular, since IoT devices are mostly in the sleep mode in the idle state, PMICs should achieve high efficiency for ultralight loads in the sleep mode as well as for heavy loads in the active mode. In this paper, an accurate bang-bang zero-current detector (to prevent a reverse inductor current) and a triple-mode switched inductor-capacitor dc-dc buck converter with a reusable flying capacitor are presented; these techniques can maintain high efficiency over a wide load current range. The proposed buck converter was fabricated in a 0.18-μm 1P4M CMOS process. A power conversion efficiency exceeding 85% was achieved in the load range of 100 µA to 300 mA.