Power Factor Correction Stage Research Articles

Modeling and Experimental Validation of Broad Input-Output Range Three-Voltage-Level Rectifier

A new type of single–conversion–step wide–input–range versatile step–up/down three–voltage–level power–factor correction stage is presented in this manuscript. The rectifier can operate both in continuous–conduction mode and discontinuous–conduction mode. First, the rectifier’s principle of operation is described, and then the innovative rectifier is analyzed in continuous and discontinuous–conduction modes. After, an average model for the innovative rectifier is developed. Lastly, the proposed theory is experimentally validated using a multiplier–less dual–control–loop mode at discontinuous–conduction modes. It is shown that although no multiplier is used in the control circuitry, the power factor is near unity. It is revealed that the rectifier can swing the output voltage from 50 V to 900 V while the input voltage is 230 Vrms. Although the rectifier output has a split DC bus with three voltage levels, the required control effort is low, and the output voltage is balanced. The innovative topology suits any standard power–factor correction rectifier application, dual–stage low–voltage power supply, and three–level voltage supplement for low–harmonic inverters. Since the rectifier’s output–voltage swing is extremely wide, energy storage systems and electric vehicle batteries are suitable applications.

Capacitance Analysis for Volume Reduction Based on Integrated Buck and Buck-Boost LED Driver

This paper presents a design methodology to improve the power density of integrated converters operating at universal input voltage fulfilling the standards of connection to the grid and load. The proposed integrated two-stage converter is composed of the power factor correction (PFC) stage behaving as a current source to the bus, and the power control (PC) stage which provides continuous energy to the LED load. Traditionally, the low-frequency ripple (LFR) filtering process is performed by the bus capacitor placed in the output of the PFC stage, while the PC stage output capacitor works only as a high-frequency (HF) filter. The idea is to explore the lower and fixed operating voltage characteristics of the PC stage to share the LFR filtering with the PFC stage. Thus, a mathematical analysis is carried out, considering the influence of the LED characteristics, bus voltage, and capacitances to predict the LFR in the LED current. A case study, composed of an integrated buck and buck-boost converter to supply a 75W LED load, is presented. For the traditional design method, the LED driver needs an 820uF/160V PFC bus capacitor and a 10uF/80V output capacitor to filter the HF components, representing a total capacitors' volume of 17.9cm³. With the proposed analysis, the optimized driver circuit requires a 220uF/160V PFC bus capacitor and a 470uF/80V output capacitor, resulting in a total capacitors' volume of 9.7cm³, providing a volume reduction of approximately 45%.

Efficiency and PF Improving Techniques with a Digital Control for Totem-Pole Bridgeless CRM Boost PFC Converters

A totem-pole bridgeless boost converter is one of the most promising topologies for the power factor correction (PFC) stage in high-power applications due to its high efficiency and small number of components. However, due to the totem-pole structure of the field-effect transistor (FET), very high switching loss occurs via the reverse recovery current of the body diode. To solve these problems, critical mode (CRM) control is a good solution to achieve the valley switching technique. With valley switching of CRM control, the switching loss decreases drastically with decreasing turn-on voltage. But, although the CRM control enables valley switching, it is hard to make an exact valley switching control with general zero-voltage detection circuits. In addition, when a frequency limitation scheme is applied to prevent a very high frequency, the switch can operate with hard switching at the boundary of the frequency limitation. Furthermore, the CRM boost PFC has a low PF and high total harmonic distortion (THD) under light-load conditions due to the large negative current resulting from resonance between the inductor and parasitic capacitance. It becomes worse at near-zero input voltage since the resonance current becomes larger near zero-input voltage. Therefore, in this paper, a totem-pole bridgeless boost PFC converter with high efficiency, high PF, and low THD is developed using TMS320F28377 by Texas Instruments. Based on the basic digital structure of the totem-pole bridgeless converter, the proposed controls help with exact valley switching, PF and THD improvement, and frequency limitation. The prototype converter is verified using 90–264 VAC input voltages and 450 V/3.3 kW output specifications.

Frequency Modulation Scheme for CCM Boost PFC Converter to Improve THD in Light-Load Condition

This study proposes a novel frequency modulation scheme for a continuous conduction mode (CCM) boost power factor correction (PFC) converter. The aim is to improve the total harmonic distortion (THD) under light-load conditions. Boost converters are widely utilized with CCM control for the PFC stage owing to their ability to achieve high efficiency with minimal components. In addition, they have a high power factor (PF) and low THD. However, despite being designed for CCM operation, the boost PFC converter transitions into discontinuous conduction mode (DCM) as the output load decreases. This mode, known as mixed conduction mode, degrades the PF and THD of the PFC converter. To address these issues, we propose a novel frequency modulation scheme. The CCM boost PFC converter adopts frequency variation to reduce the DCM region. To validate the feasibility of the proposed concept, a prototype with a 60 Hz/230 Vac input and 850 W/380 V output was utilized. Consequently, the boost PFC converter attains a high PF and low THD with simplified circuits.

LLC Resonant Converters as Isolated Power Factor Corrector Pre-Regulators—Analysis and Performance Evaluation

The power supply of many applications running off the power line is made up of an isolated dc-dc converter powered by a front-end power factor corrector (PFC) stage. The PFC stage ensures compliance with the electromagnetic compatibility regulations but does not usually provide safety isolation since it is typically implemented with a boost converter. Lately, the increase in multi-output power supplies, especially in lighting and USB Power Delivery applications, has raised the need for an isolated PFC at power levels where currently there is not an industry standard solution. This isolated PFC is intended to power one or more non-isolated post-regulators to enable a substantial simplification of the overall architecture and a cost reduction. The usage of an LLC resonant converter as an isolated PFC has been considered and demonstrated only quite recently, raising the industry’s attention due to the favorable converter’s characteristics that have led to its success as a dc-dc converter. This paper provides two significant contributions. Firstly, it provides a quantitative assessment of the difference in the results obtained by designing an LLC-based PFC converter based on the first harmonic approximation analysis or the time-domain analysis by applying them to the design of the same converter. Secondly, it demonstrates that designing an LLC-based PFC converter to work also in the above-resonance region optimizes its performance by reducing the (magnetizing) reactive current in the resonant tank and, therefore, the rms currents on both the input and the output side and the related power loss.

Star Power Factor Correction Architecture

Conventional two-stage power factor correction (PFC) architecture based on a boost PFC front end and an isolated dc–dc back end is increasingly challenged by the recent trend toward higher power density and efficiency. One key reason for the challenge is the difficulty of increasing the operating frequency of the boost PFC stage. This article presents a new star PFC architecture that allows the boost PFC stage to operate efficiently at a higher frequency while maintaining the performance of the second dc–dc stage, leading to a high-power-density and high-efficiency ac–dc converter design across a universal input. The high performance of star architecture is enabled by realizing: 1) continuous-conduction-mode (CCM) operation of the boost PFC stage; and 2) full-range zero-voltage-switching (ZVS) of all active switches. In addition, the star architecture can: 1) operate at a constant frequency via a proper selection of the circuit topology and modulation method; and 2) be controlled based on simple and low-cost analog circuits. A 300-kHz, 240-W, 48-V-output, and universal-input prototype is built to verify the performance of the star architecture, showcasing high power factor, constant output voltage, 97.1 % full-load efficiency, 55.6 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> power density by box volume.

Efficient Soft Switching Single-Stage PFC for Low-Power Applications

Single-stage (SS) power factor correction (PFC) converters are applied as the power supply for low-power devices. Usually, the flyback converter is merged with the PFC stage to eliminate the reset winding required for the transformer. This article merges a new resonant forward converter with the buck-boost PFC stage. Thus, reset winding of the forward converter is eliminated while soft switching is achieved. Due to the low flux of the forward transformer core, transformer volume is reduced. Also, for the same volume of the transformer, transformer losses can be reduced in comparison to the flyback converter. The proposed converter is analyzed, and design considerations are discussed. A prototype converter is implemented. According to the experimental results, high efficiency and low total harmonic distortion (THD) are achieved.

Design, modelling, and simulation of bridgeless SEPIC-fed three-level soft switched converter for EV battery charging

ABSTRACT This paper discusses the design and analysis of a three-level LLC (TL-LLC) resonant converter for an electric vehicle (EV) charging application. The proposed two-stage onboard charger comprises an ac-to-dc power factor correction (PFC) stage, followed by the second stage required to provide galvanic isolation and dc-to-dc conversion. The PFC stage uses a bridgeless SEPIC converter with average current control and voltage mode control algorithm for achieving unity power factor (pf) operation with constant DC link voltage. In contrast, the dc/dc stage uses a three-level LLC resonant converter with a frequency control algorithm to control the output voltage. A 1 kW, 360 V output model of the proposed onboard charger is implemented and simulated in PSIM, and the obtained results are investigated and examined in detail. Results obtained from the simulation show a power factor greater than 0.99 with THD less than 5 at the input side. For TL-LLC, both zero voltage switching (ZVS) for primary MOSFETs and zero current switching (ZCS) for secondary side rectifier diodes are achieved.

Reducing Low-Frequency Ripple Using Alternative Output Capacitor Connection on Integrated Converters for LED Drivers

Although advantageous in several aspects, the integration of converters leads to a loss of independence between the converter's stages, since both stages are controlled by the same active switch. This condition makes it impractical to adopt control techniques that act on the duty-cycle to mitigate the low-frequency ripple at the output current without distorting the line current. The low-frequency ripple transferred from the bus voltage to the LED current has been studied for integrated converters operated at constant duty-cycle. To comply with IEEE 1789-2015 recommendation, the integrated converters use large capacitors to mitigate the low-frequency ripple. Converters operating in discontinuous conduction mode (DCM) have been widely adopted because they transfer less ripple to the output than converters operating in continuous conduction mode (CCM). A novel circuit arrangement for the buck-boost power control (PC) stage integrated with a buck-boost power factor correction (PFC) stage is explored in this paper as a technique to minimize the low-frequency output ripple for converters operating at constant duty-cycle and CCM. The proposed circuit provides current feedback to the bus capacitor, acting to reduce the output current and bus voltage low-frequency ripple. A dynamic model for the proposed converter in CCM is obtained and used to determine the output current modulation as a function of converter parameters. It is shown that the proposed topology leads to a smaller low-frequency ripple than a conventional counterpart at the same operating point. A 95 W design example and a prototype supplying an LED load of 98.8 V / 960 mA for the proposed circuit and the conventional counterpart are presented. The experimental results show that the proposed arrangement can achieve similar results to the conventional circuit in efficiency, THD, or semiconductor stress, while the obtained output current modulation equals to 8.66 % is 3.5 times lower than that in the conventional circuit at same operating point and component values.

An Integrated Single-Stage Single-Switch Topology With Reduced Nonlinear Components for LED

This article presents an integrated single-stage single-switch (4S) ac–dc system for LED delivering a high input power factor (IPF) and regulated output. The proposed topology integrates a power factor correction (PFC) converter with a high-frequency dc–dc converter, driven by a modified front-end single-phase Vienna rectifier. The integration results in a single switch prototype, thus decreasing the cost and complexity of the control circuit. The use of fewer diodes in the front-end rectifier reduces the nonlinearity in the proposed topology. First-stage filter capacitors offer a better input dynamics to the PFC stage. The proposed (4S) prototype offers less component counts and minimal input current harmonics. The theoretical and mathematical analysis of the proposed topology is presented. Finally, the proposed (4S) ac–dc system analysis and simulation results have been verified with a 50 W/60 V prototype depicting an IPF of 0.997, total harmonic distortion (THD) of 3.96%, and an efficiency of 90.8%. The presented experimental results coincided with the analysis and comply with IEC61000-3-2 standards.

Academic Use of Rapid Prototyping in Digitally Controlled Power Factor Correctors

The growing use of power converters connected to the grid motivates their study in power electronics courses and the prototype development in the degree final project (DFP). However, the practical realization of using state-of-the-art components and conversion techniques is complex due to the numerous multidisciplinary aspects that students must consider in its design and development and the workload associated with the DFP. An example of this is that, unlike a conventional power factor correction (PFC) design, the individual dedication of students to complete the design and validation of modern bridgeless PFC stages exceeds the number of credits of the DFP. The reason for this is that it includes system modeling, becoming familiar with the devices used, discrete selection, circuit design, control development, and programming, to build the converter and verify the operation of the complete system. To reinforce the individual skills needed for the DFP and reduce this time, a novel strategy is proposed. It allows the student to focus their efforts on integrating the individual skills achieved in the degree at the appropriate competence level during the modeling and construction of the power converter while carrying out part of the tasks out of the lab, if necessary, as was the case during the pandemic restrictions. For this, the rapid prototyping technique is introduced to speed up the overall design and speed up the tuning of digital controllers. This manuscript presents a teaching experience in which students build digitally controlled power converters using Texas Instruments microcontroller boards and PLECS®. The example of a bridgeless totem-pole power factor corrector is shown. Although it began to develop and was motivated due to the restrictions during the COVID-19 pandemic, the experience has been verified and is maintained over time, successfully consolidating.

Non-Isolated Power Factor Corrected AC/DC Converter with High Step-Down Voltage Ratio for Low-Power Applications

This paper proposes a high step-down ratio AC-DC converter employing a quadratic buck converter with power factor correction. Conventional active power factor correction topologies employ boost-based correction schemes for unity power factor operation. This will require a steeper step-down ratio and higher switch voltage stress apart from complexity in the control scheme with sensors. The structure of the proposed topology is developed by combining the power factor correction stage with a high step-down stage. The passive input filter is split up into two for the purpose of reducing the thermal heating apart from offering a higher power factor. A single switch operation reduces the complexity of the control scheme. In addition, the number of conducting devices during the current path is also the same as the conventional buck converter due to cascading and hence offers lower conduction losses. The need for the converter to operate at an extremely low duty cycle is reduced due to the quadratic stage structure. The proposed converter operates at a moderate duty cycle, offering higher step-down voltage apart from reducing filtering requirements. MATLAB R2020b is used for carrying out simulation studies. Xilinx FPGA-based controller using system generator is implemented for the generation of pulses of appropriate duty cycle. Simulation and experimental results for a 150 W prototype are presented. An investigation and comparative evaluation of the conventional bridgeless buck system with the quadratic buck converter are carried out. The proposed structure offers the benefit of a higher step-down voltage ratio incorporating an inherent power factor correction stage along with the AC/DC stage.

Design and Implementation of Power Supply for Ventilator

Abstract: DC-DC Converters are the inevitable stage in a system to power-up an electronic device, as it is very prominent to obtain a regulated and constant dc-dc supply to most of the electronic devices. These dc-dc converters are supplied with the dc supply either given directly by dc sources like batteries or obtained by converting AC to DC supply. In the proposed project, firstly the single phase ac supply of 230V,50 Hz is boosted to 390V DC and concurrently the power factor of the supply is corrected in the Boost Power Factor Correction (PFC) stage using IC UCC28180 which constitutes the first stage of the project. Further, this DC voltage is given to the Forward converter where it is stepped down to 48V DC which is finally given to power-up the ventilator. The designing of both Boost and Forward converters is done and they are verified by simulating them in the MATLAB Simulink software platform. Hardware implementation with the designed values is done and the relevant waveforms are obtained.

절연형 고전력 밀도 통신 DC-DC 컨버터 스테이지용 자기 전력 부품 설계 분석 및 제조

The adoption of 5G technology in communications necessitates an increase in supply power factor and conversion efficiency to improve power quality. A two-stage AC-DC power supply with a power factor correction (PFC) stage and a DC-DC converter stage is the best option for supplying power to these loads, with the PFC stage

A High-Power-Density High-Efficiency Soft-Switched Single-Phase Universal Input to 28-V Isolated AC–DC Converter Module Designed for Paralleled Operation

This article presents a high-power-density high-efficiency soft-switched single-phase universal input to 28-V isolated ac–dc converter module designed for parallel operation. The proposed two-stage converter utilizes a totem-pole bridgeless boost power factor correction (PFC) ac–dc converter stage followed by an isolated <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> resonant dc–dc converter stage. A comprehensive design and optimization methodology is presented that compares various designs and operating modes for the converter's power stages and selects the optimal design based on overall power density and efficiency. Additionally, a control scheme is presented for the PFC stage to minimize current distortion by accounting for various sensor, control, and gate-drive delays while ensuring zero-voltage switching (ZVS) of the transistors. Moreover, a new droop control strategy is presented, which utilizes the input current of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> dc–dc stage to ensure equal output current distribution between paralleled modules powering a common output load. To validate the proposed design and control strategy, two 1-kW universal input to 28-V isolated ac–dc converter modules are built and tested. Each prototype converter module achieves a high power density of 84 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> and a peak efficiency of greater than 93% while ensuring a current distribution error of less than 0.3% when operating in parallel to deliver the maximum output power of 2kW.

Design and Fabrication of an Isolated Two-Stage AC–DC Power Supply with a 99.50% PF and ZVS for High-Power Density Industrial Applications

Power quality in terms of power factor (PF), efficiency, and total harmonic distortions (THDs) is an important consideration in power supplies designed for 5G telecom servers. This paper presents a different magnetic parts design and manufacturing techniques of power supplies, design and selection criteria of switching elements as well as the optimal design of control loops based on small-signal stability modeling and an appropriate stability criterion. The designed telecom power supply consists of the power factor correction (PFC) stage to increase the input power factor and the isolated phase-shift pulse width modulation (PWM) zero-voltage switching (ZVS) DC–DC converter stage to regulate the supply voltage to the specified load value while maintaining a high conversion efficiency. A two-stage outdoor telecom power supply with a power rating of 2 kW was designed and fabricated on a printed circuit board (PCB). The distinct two-stage power components of the power supply were subjected to loss analysis. Furthermore, PSIM simulation and experiments were used to demonstrate the total harmonic distortions (THDs), voltage ripples, power efficiency, and PF performance of the supply current for the proposed power supply under various operating situations. This work produces an industrial high power density power supply with a high PF, low THD and high conversion efficiency which is suitable for telecom power server applications.

유도 부하에 적합한 넓은 입력 전압 범위와 높은 역률의 2단 AC-AC 컨버터 설계

In this paper, a two-stage AC-AC power supply is designed to specifically handle the operation and performance improvements of the power system with highly inductive loads. The proposed power supply scheme includes an input interleaved power factor correction (PFC) stage to improve the input power factor (PF) and regulate the DC bus voltage required for the second stage, which is a voltage source inverter (VSI) with an output low pass filter to adjust the load harmonics contents and regulate the load voltage and frequency to the specified AC load values. The small-signal models of the PFC and VSI stages are obtained, and optimal voltage and current control loops for both stages are designed based on the obtained models to improve the required system power performance and stability. PSIM simulation is used to examine the performance of the proposed power supply under various input-output operation conditions. This work achieves a 500VA, (180-260)V RMS Power supply with an input PF of 99%, better output voltage regulation, and a lower THD value for the purpose of supplying industrial inductive loads.

Power factor correction stage and matrix zero voltage switching resonant inverter for domestic induction heating appliances

Power factor correction stage and matrix zero voltage switching resonant inverter for domestic induction heating appliances

Review of the CM noise mitigation methods for the single-phase power factor correction converter

Several techniques to mitigate conducted electromagnetic interference (EMI) in single-phase power factor correction (PFC) converters have been reported in literatures. This paper mainly focuses on the review and classifications of the common-mode (CM) noise mitigation methods based on the novel structures, balance concept, novel modulation methods and so on. Through eliminating the noise generation or cut off the propagation path, those methods can mitigate the CM noise caused by the single-phase PFC converter. Besides, the comparisons and limitations are also discussed. It is believed that this review will be helpful to the design of the EMI filter for the switch-mode power system, which includes the PFC stages.

12-Pulse Rectifier with Two DCM Boost-Type Half-Controlled Bridges for Variable- Input-Frequency Applications

This paper presents the analysis of the integration of two three-phase half-controlled boost converters, operating in discontinuous conduction mode (DCM), to the auto-connected 12-pulse rectifier. The proposed structure shows a reduced current harmonic content compared to the traditional 12-pulse rectifiers, being a simpler and effective alternative to using rectifiers with higher pulse numbers. It also presents a greater range of possibilities for regulating the output voltage, without the use of synchronization algorithms or rigorous control techniques, being possible to send to all controlled switches, the same command signal, resulting in a simpler logic. Another advantage of using the proposed technique is the employment of a single-loop voltage control scheme, reducing the computational and financial cost by eliminating some elements such as current sensors. Moreover, the proposed strategy provides soft commutations (Zero-Current-Switching - ZCS). In this work, a small-scale prototype was implemented, aiming to obtain a structure capable to operate in a wide range of line frequencies, without requiring any additional complex techniques. In this regard, the developed structure is capable to work as a Power Factor Correction (PFC) stage in a wide range of input frequencies (30Hz - 120Hz) with a Total Harmonic Distortion of the input current (THDi) of less than 2.19%.