Power Factor Correction Cell Research Articles

Single-Stage Boost-Buck PFC Converter with Soft-Switching Operation and Ripple-Free Output Current

In this paper, a single-stage boost-buck power-factor-correction (PFC) converter with soft-switching operation and ripple-free output current is proposed. In order to obtain high power factor, a boost PFC cell is operated in discontinuous conduction mode (DCM) with a fixed switching frequency according to the load condition. For the ripple-free output current, a buck inductor is replaced with a coupled inductor and an auxiliary capacitor. The boost PFC cell and the buck converter share a main switch and a self-driven synchronous rectifier (SR). By turning the SR off after a short delay, the main switch is turned on under zero-voltage-switching (ZVS) condition. Since the conduction loss on the SR is reduced and there is no switching loss on the main switch, the power-conversion efficiency is improved. The maximum efficiency of the proposed converter 93.37% is measured at 130vac. To verify the performance of the proposed converter, theoretical analyses, design procedures, and experimental results from a 80V and 100W prototype are presented.

A Novel PCCM Voltage-Fed Single-Stage Power Factor Correction Full-Bridge Battery Charger

A novel pseudo-continuous conduction mode (PCCM) voltage-fed single-stage power factor correction (PFC) full-bridge battery charger is proposed in this paper. By connecting a freewheeling transistor in parallel with an input inductor, the PFC cell can operate in the PCCM with a constant duty ratio. Thus, the dc/dc stage can be designed using this constant duty ratio and the restriction on the duty ratio of the PFC cell is eliminated. As a result, the input current distortion is less and the dc bus voltage becomes controllable over the wide output power range of the battery charger. Moreover, the operation principle of the dc/dc stage is designed to be similar to that of a conventional phase-shifted full-bridge converter. Therefore, it is easy to implement. In this paper, the operation of the new converter is explained, and the design considerations of the controller and key parameters are presented. Simulation and experimental results obtained from a 1 kW prototype are given to confirm the operation of the proposed converter.

Efficient Single-Switch Boost-Dual-Input Flyback PFC Converter With Reduced Switching Loss

This paper presents an efficient single-switch boost-dual-input flyback power factor correction (PFC) converter. To achieve a high power factor, a boost PFC cell operating in discontinuous conduction mode is presented. A dual-input flyback dc–dc module, which consists of parallel primary windings and serial secondary windings, operating in critical conduction mode is introduced for galvanic isolation and valley-switching operation. In addition, the proposed converter features high efficiency because the input power is equally divided, and some power is directly transferred to the load by the dual-input flyback dc–dc module. The remaining power is stored in dc-bus capacitors, and it is closely related to the holdup time. Moreover, the currents in the leakage inductors are absorbed by the dc-bus capacitors through a snubber diode, and they are reprocessed by the dual-input flyback dc–dc module. Consequently, the peak voltage in the MOSFET drain is clamped, and the total power conversion efficiency is improved. To verify the performance of the proposed converter, the operating principles, steady-state analysis, and experimental results from a 48 V, 100 W prototype are presented.

Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters

Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to save power losses. This letter addresses this problem by using a buck topology for the PFC stage of the single-stage single-switch converters as it can be completely turned OFF by operating the converter only near the zero crossing of the input voltage, due to the presence of the dead angle of input current. Hence, the switching and conduction losses to the transistor and diodes, and passive devices are reduced. Also, further improvement is made by finding the best combination of dc-bus capacitor charging time and discharging time to achieve the lowest power loss. A recently proposed converter topology which combines a buck PFC cell with a buck-boost dc/dc cell is used as an example. Experimental results are reported and confirmed that the proposed light-load power loss reduction scheme on the converter can improve power stage efficiency by up to 7% at 1 W of output power as compared to that without the proposed scheme.

VLSI Design and Application of a High-Voltage-Compatible SoC–ASIC in Bipolar CMOS/DMOS Technology for AC–DC Rectifiers

This paper presents an application-specific integrated circuit (ASIC) controller that is suitable for double-stage AC-DC power converters, which employ power-factor correction (PFC) and flyback topologies. The PFC cell is used as a preregulator to comply with line-current harmonic standards, while the flyback converter operates in quasi-resonant (QR)/discontinuous conduction mode to deliver to the load a maximum output power of 120 W. The control functions of the PFC and flyback converters are combined in a unique system-on-chip-ASIC solution to reduce system complexity. The ASIC implements valley-switching control of both the PFC and flyback cells to achieve QR operation. The concept of ldquovalley skippingrdquo is also recalled by the proposed ASIC to determine the operating point in the power-frequency characteristic of the power converter. Depending on the output-power requirement, the ASIC drives the flyback stage into three different states, which result from the combination of the QR and valley-skipping modes. This allows the flyback converter to operate at a fixed on-time, while its off-time is changed according to the output power. The PFC stage is also driven in the QR mode with valley skipping to provide the DC-DC stage with a fixed input voltage of 400 V. To evaluate the performances of the presented ASIC device, a demoboard of a 120-W PFC-flyback system has been realized and tested. Several experimental results have been carried out to confer the validity of the approach that is discussed throughout this paper and to evaluate the performances of the AC-DC rectifier.

Flyboost Power Factor Correction Cell and a New Family of Single-Stage AC/DC Converters

A novel power factor correction (PFC) cell, called flyboost, is presented. The proposed PFC cell combines power conversion characteristics of conventional flyback and boost converters. Based on the flyboost PFC cell, a new family of single-stage (S/sup 2/) ac/dc converters can be derived. Prominent features of newly derived S/sup 2/ converters include: three power conversions, i.e., boost, flyback, and another isolated dc/dc power conversions are simultaneously realized that typically uses only one power switch and one simple controller; part of the power delivered to the load is processed only once; bulk capacitor voltage can be clamped to the desired level; and capable of operating under continuous current mode. Experimental results on example converters verify that while still achieving high power factor and tight output regulation, the flyboost PFC cell substantially improve the efficiency of the converter.

An alternative approach to synthesizing single-stage converters with power-factor-correction feature

An alternative approach to synthesizing single-stage converters (SSCs) with power-factor-correction (PFC) feature is presented in this paper. The proposed approach is primarily based on the concept of dither effect, from which PFC cells composed of energy buffers and high-frequency dither signals are introduced. Properly selecting an eligible PFC cell and inserting it in between input rectifier and DC-link capacitor can yield an SSC which can improve the input power factor significantly. In this paper, principle and configuration of PFC cells are addressed; thus, quite a few families of SSCs can be synthesized from the derived PFC cells. With this approach, not only can the SSCs discussed in the literature be developed alternatively, but novel SSCs can be synthesized. Most of the SSCs have been proved in the literature to be feasible in applications with moderate power levels.