Power Electronics Packaging Research Articles

C-BAND PULSED SOLID STATE POWER AMPLIFIER FOR SPACEBORNE APPLICATIONS

The basic applications of pulsed solid state power amplifler are for airborne and spaceborne pulsed Radar and these applications have always demanded well performance over difierent environmental conditions. The success of the electronic systems for these applications relies on the ability to design high performance; reliable and high yield circuits, which will function against the demanded environmental speciflcations. This paper describes the detailed design and development of a spaceborne C-band pulsed solid state power amplifler to deliver 12-watt output power, 45dB gain with 22 microsecond pulse width and 8% duty cycle. The salient features of this paper are drain modulated pulse driver circuit design, non- linear design of the power stages and electronic package design. The paper also describes pulsed SSPA conflguration, RF section, Electronic Power Converter Module, RF design and other space aspects to realize the pulsed solid state power amplifler. It is fabricated on the three- layer metallized alumina substrate, integrated with power converter module; and tested under simulated space environment. The test result validates the design speciflcation of the pulsed solid state power amplifler, implemented at miniaturized conflguration.

Transfer molding technology for smart power electronics modules - materials and processes

During the last years within power electronics packaging a trend towards compact power electronics modules for automotive and industrial applications could be observed, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics yielding maximum miniaturization. Transfer molding is the method of choice for cost effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package: Typically those packages are asymmetric, a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed providing a heat path for optimized cooling. This asymmetric geometry is prone to yield warped substrates, preventing optimum thermal contact to the heatsink and also putting thermomechanical stress on the encapsulated components, possibly reducing reliability. Such packages being truly heterogeneous, combining powerICs, wire bonds, SMDs, controlICs, substrate and leadframe surfaces, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally those packages need to operate at elevated temperatures for increased times, e.g. operate at 150 °C for 2000 h and more, so high thermal stability is of ample importance. Within this paper a reference application is described, integrating power and control logic inside a leadframe based molded package. Taking into account the challenges mentioned above, a detailed description of material selection for this module will be given, including material analysis as rheology, reactivity, change in ɛr and thermomechanical properties as f(t,T) and of media storage. Process development tools for module molding are used to ensure manufacturability and useability. Concluding rules for encapsulant material selection and package setup are provided.

Technologies and Trends to Improve Power Electronic Packaging

In the realm of power modules a strong trend toward high temperature and high reliability applications can be observed, which entails new technological challenges, especially for the assembly and packaging of power semiconductors. Because of the well known failure mechanisms of established lead-free standard soldering and heavy aluminum wire bonding technologies, such as fatigue and creep of die attach material and wire bonds at thermal cycling, academic and industrial research focuses on more reliable interconnection technologies. A priority is the research of alternative top and bottom side chip interconnection materials or technologies to improve the temperature cycling capability of power chips that are typically assembled on ceramic substrates. The scientific focus is on Ag sintering as die attach and/or heavy ribbon bonding, for example with Al or bi-metal (Al-Cu). Another focus is the material behavior of ribbon bonds in combination with bonding machine improvements (higher bonding parameters, cutting tool). But there are other very promising technologies like transient liquid phase bonding, for example with Cu-Sn or Ag-Sn systems or Cu heavy wire bonding (up to 400 μm wire diameter) or Cu/Al-Bi metal ribbon bonding. Challenges posed by these technologies have to be discussed focusing on materials and process selection and reliability issues. Process temperatures and temperature profiles must be optimized, wire bonding machines and the chip surface structures as well as finish metallizations need to be adapted. This paper will give an overview of alternative power chip interconnection technologies and discuss the challenges related to processing and reliability.

Analysis of thermoelectric cooler performance for high power electronic packages

Abstract In this paper, an analysis of thermoelectric cooler (TEC) performance is conducted for high power electronic packages such as processors. Based on the TEC module parameters, two sets of analytical solutions for TECs in system constraints are derived for the junction temperature T j at a fixed cooling power Q c , and for Q c at a fixed T j , respectively. As against the iterative procedure often reported in literature, the major advantage of the present analytical method lies in the fact that the solutions can be obtained without resorting to the pellet thermoelectric parameters and geometric details. Two cooling scenarios, the processor test and the processor cooling under end-user conditions, are analyzed based on the present analysis models for two commercial TECs with high cooling power capacities nominal. Analytical results show that significant thermal enhancements are achievable based on optimized currents and cooling configurations. The validation of the present analysis is also conducted through experimental measurements and comparison with previous solutions.

Design for reliability of power electronics modules

Power electronics uses semiconductor technology to convert and control electrical power. Demands for efficient energy management, conversion and conservation, and the increasing take-up of electronics in transport systems has resulted in tremendous growth in the use of power electronics devices such as Insulated Gate Bipolar Transistors (IGBT’s). The packaging of power electronics devices involves a number of challenges for the design engineer in terms of reliability. For example, IGBT modules will contain a number of semiconductor dies within a small footprint bonded to substrates with aluminum wires and wide area solder joints. To a great extent, the reliability of the package will depend on the thermo-mechanical behavior of these materials. This paper details a physics of failure approach to reliability predictions of IGBT modules. It also illustrates the need for a probabilistic approach to reliability predictions that include the effects of design variations. Also discussed are technologies for predicting the remaining life of the package when subjected to qualification stresses or in service stresses using prognostics methods.

Visual Prosthesis

Electronic visual prostheses have demonstrated the ability to restore a rudimentary sense of vision to blind individuals. This review paper will highlight past and recent progress in this field as well as some technical challenges to further advancement. Retinal implants have now been tested in humans by four independent groups. Optic nerve and cortical implants have been also been evaluated in humans. The first implants have achieved remarkable results, including detection of motion and distinguishing objects from a set. To improve on these results, a number of research groups have performed simulations that predict up to 1000 individual pixels may be needed to restore significant functions such as face recognition and reading. In order to achieve a device that can stimulate the visual system in this many locations, issues of power consumption and electronic packaging must be resolved.

Heat Pipe Integrated in Direct Bonded Copper (DBC) Technology for Cooling of Power Electronics Packaging

Thermal dissipation in power electronics systems is becoming an extremely important issue with the continuous growth of power density in their components. The primary cause of failure in this equipment is excessive temperatures in the critical components, such as semiconductors and transformers. This problem is particularly important in power electronic systems for space applications. These systems are usually housed in completely sealed enclosures for safety reasons. The effective management of heat removal from a sealed enclosure poses a major thermal-design challenge since the cooling of these systems primarily rely on natural convection. In this context, the presented paper treats the heat pipes as effective heat transfer devices that can be used to raise the thermal conductive path in order to spread a concentrated heat source over a larger surface area. As a result, the high heat flux at the heat source can be reduced to a smaller and manageable level that can be dissipated through conventional cooling methods. The objective of our work is to describe the feasibility of a cooling system with miniature heat pipes embedded in a direct bonded copper (DBC) structure. The advantage of this type of heat pipe is the possibility for implementation of the component layout on the heat pipe itself, which eliminates the existence of a thermal interface between the device and the cooling system

An integrated methodology for multiobjective optimal component placement and heat sink sizing

The advances in power electronics packaging resulting from the integration of various high power devices into single programmable blocks are projected to significantly increase heat dissipation rates up to 2-3 W/mm/sup 2/ within the next decade. Conventional thermal management schemes such as air-cooled heat sinks are inadequate at these high power levels, requiring the use of forced liquid cooled heat sinks, or cold plates. A primary issue concerning the thermal-packaging designers today is the selection of a suitable cold plate and the optimum placement of components on it. This paper focuses on a methodology for selection of cold plates and the optimal placement of power modules on them. The basis of the methodology is the integration of computationally efficient reduced or "compact" thermal models within a genetic algorithm based multiobjective optimization framework. This methodology is used to optimize the placement of multiple power modules on a cold plate. It is also extended to perform a tradeoff analysis between multiple competing objectives for cold plate selection. Compact thermal models for power electronics and heat sinks are developed, validated, and integrated within the optimization framework. The effectiveness of the methodology as a rapid scouting tool to arrive at an optimum tradeoff solution set for further analysis by detailed numerical simulation is discussed. The methodology is general in the sense that it allows for incorporation of changes in optimization criteria or improvements in the heat transfer solver.

1306 製品開発における新しいシックスシグマ : 高機能パワーユニットの信頼性設計(CO2 設計コンテストI)

1306 製品開発における新しいシックスシグマ : 高機能パワーユニットの信頼性設計(CO2 設計コンテストI)

Real-Time Computation of Thermal Constraints in Multichip Power Electronic Devices

In this paper, we present an implementation of a thermal modeling method, based on thermal impedances analysis and applied to a multichip module used as a power converter. Analytical functions of thermal impedances are derived from direct measurements of chips temperature with optical fiber sensors. We describe an original algorithm with a recurrent procedure to compute directly and accurately the convolution integrals with high speed performances. Finally, experimental measurements, in real working conditions, have been performed in order to complete the validation of the real-time estimation of the junction temperatures of the power electronic package.

STUDY OF BONDED PLASMA-TREATED POLYETHERIMIDE COMPONENTS FOR POWER INTEGRATION: DURABILITY IN A HOT/WET ENVIRONMENT

This work deals with the study of the durability, in a hot/wet environment, of structural adhesively bonded polyetherimide (PEI) assemblies used in power electronics packaging technology. An overall approach is proposed, for which the epoxy joint-PEI substrates assembly on the one hand, and the adhesive system components (substrate surface and bulk adhesive) on the other hand, are studied separately with different analytical techniques. The first part of this work was devoted to the substrate surface state and to its modification using a cold plasma treatment of the PEI surface. Then for chosen parameters (power, duration) contact angle measurements indicated an increased surface tension resulting from surface decontamination (removal of release agent and carbon contaminants) and from the creation of polar species, such as esters or carboxylic acid groups, on the PEI surface (XPS analyses). The second part of this study concerned the bulk adhesive ageing in an ethylene glycol-water solution at 70°C. Mass uptake measurements versus time showed the liquid diffusion in the bulk adhesive associated with a microscopic damage of the epoxy system. An overall plasticizing of the adhesive with a considerable decay of the α-transition temperature of one of the two adhesive epoxy-amine networks (TGDDM-BAPP) was also highlighted using rheometry. However, in these ageing conditions, the adhesive glassy modulus decreases slighty because of the thermomechanical stability of the other epoxy network. In the third part, the asymmetric wedge test showed the beneficial effect of the cold plasma treatment on the epoxy/PEI interface durability in the aggressive medium.

An Approach To Numerical Simulation Of Thermal Contact Problems In Modern Electronic Packages

The increasing demand on higher packaging density, higher frequency and higher power of the electronic devices is a challenge for contemporary engineers to be able to simulate and prototype as mechanical as thermal problems. The heat dissipation problem is becoming nowadays a crucial issue and requires application of materials with high thermal conductivity and novel packaging methods. Currently there are a number of recognised “bottle necks” for heat dissipation in electronic packages. One of them is a thermal contact resistance (TCR), which arises in the region where two solid contact members touch each other. The high TCR reduces the amount of heat which can be transmitted from the heat source to the heat sink and the same raises the device temperature and reduces the overall reliability of the package due to thermo-mechanical stresses. There have been a large number of theoretical and experimental investigations performed to understand and improve the knowledge on TCR. The TCR arises in the region of contact, when two solids are pressed together. The real contact area is only a small fraction of the nominal or apparent area [1]. Despite of the profound studies not fully understanding and satisfactory method has been elaborated to be able to predict with reasonable accuracy the heat conduction across the contact. Besides, the thermal properties of TCR are not known and only some assumptions are made to be able to simulate the temperature distribution over electronic packages with the TCR existence. In this paper a combined experimental-numerical approach to the simulation of thermal contact problems in electronic package is applied. The test results revel that the approach can be a promising solution allowing for quick verification and evaluation of temperature distribution in high power electronic packages, which seem to be crucial nowadays.

High-Performance Packaging of Power Electronics

AbstractPackaging of solid-state power electronics is a highly interdisciplinary process requiring knowledge of electronics, heat transfer, mechanics, and materials science. Consequently, there are numerous opportunities for innovations at the interfaces of these complementary fields. This article offers a perspective of the current state of the art and identifies six specific areas for materials-based research in power electronics packaging. The emphasis is on identifying the underlying physical relationships that link the performance of the power electronics system to the microstructure and architectural arrangement of the constituents.

Flywheel batteries come around again

Today's flywheel batteries, embody technological advances, and they are serious contenders for a variety of important energy-storage applications. They are, for example, competitive with chemical batteries in applications like transportation or improving power quality, which involve many charge-discharge cycles and little in the way of long-term storage. Progress in power electronics, particularly in high-power insulated-gate bipolar transistors (IGBTs) and field-effect transistors (FETs), underlies higher-power flywheel operation. While the stored energy is determined by the speed, mass, and geometry of the wheel, the limits on input and output power are in general set by the power electronics. With these higher power devices, fewer individual components are needed, so the power electronics package can be comparable in size to the flywheel plus motor-generator combination. This paper describes the main features of flywheel energy storage systems and space, hybrid electric vehicle, and combat vehicle applications.

Benchmark of power packaging for DC/DC and AC/DC converters

This paper presents the first reported final results of a benchmarking project "StatPEP" which investigated the Status of Power Electronic Packaging used in commercial DC/DC and AC/DC switch mode power supplies. The methodology of the project is first described. Some of the salient results of a comprehensive benchmarking of DC/DC converters (rated power of 100 W) and AC/DC converters (rated power up to 576 W) are presented. Examples for figures-of-merit are presented. The results of the investigation are presented in a generic form, which does not identify individual products. A comparison of the performance of the units shows that the measured power density of the AC/DC units is approximately 10% that of the DC/DC while the thermal density based on footprint is 50%. Also the switching frequency of the AC/DC is 50% that of the DC/DC. Some of the reasons for these differences are discussed.

Failure modes and FEM analysis of power electronic packaging

The development of power electronics technology is driven by the insatiate demand to control electrical power. The new power electronics devices reduce the volume of the converters by three to four orders of magnitude compared to their mercury arc predecessor. And the turn-on and turn-off time has decreased from milliseconds to the microseconds and even nanoseconds, depending on power level. The power range commanded by converters now extends from micro-VA to several hundreds of mega-MVA. Among the new power devices, insulated gate bipolar transistor (IGBT) devices are being more accepted and increasingly used in traction application such as locomotive, elevator, tram and subway. Thus the long-term reliability of IGBT is highly demanded. In this paper the failure modes of power electronics devices especially IGBTs are reviewed. A FEM analysis of a multilayered IGBT packaging module under cyclic thermal loading is presented.

Chip-scale packaging of power devices and its application in integrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D/sup 2/BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D/sup 2/BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V/sub CE/(sat) and on-resistance of the D/sup 2/BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D/sup 2/BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported.

Reliability model for Al wire bonds subjected to heel crack failures

In power electronic packages wire bonding is used for the electrical contact of the chips and for interconnections on the module substrate. Limiting factors for the reliability are solder fatigue and wire bond failures. In this work we investigate the material fatigue of aluminum bonding wires stressed by cyclic lateral bonding area displacement. Bond wire heel crack failures observed by experiments are found to be strongly dependent on the loop geometry. Based on a finite element model that accounts for elastic-plastic material properties, a life-time model for the Al wire (Coffin-Manson representation) is derived from the experiments.

Thermal management of high power electronics with phase change cooling

A study on the prospect of designing high power electronic packages with phase change cooling is presented, with special emphasis on minimising the rising of junction temperatures due to thermal transient effects. The one-dimensional thermal model consists of a finite slab suddenly exposed to a uniform heat flux at the top surface and cooled by convective air at the bottom. The phase change problem is divided into sub-problems and solved progressively. Before the slab starts to melt, both exact and approximate solutions are presented for the distribution of temperature in the slab as functions of time and Biot number Bi. The necessity of partitioning the time domain into two regimes, separated by the time t0 needed for the thermal front to traverse across the whole slab, is emphasised. After the slab melts, quasi-steady state solutions are obtained both for the melt depth and the evolution of surface temperature as functions of time and Biot number when tm>t0, with tm denoting the time needed for melting to commence at the top surface of the slab. The quasi-steady state solutions are compared with those obtained by using the method of finite elements. Approximate but simple analytical solutions are also constructed for the tm<t0 case which, again, are compared with the finite element results. Finally, these solutions are analysed to guide the design of advanced packages with optimised phase change cooling strategies.

Power Electronics Package (Self-Study Course) [Advert

Power Electronics Package (Self-Study Course) [Advert