Power-down Technique Research Articles

A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique

A high-resolution dynamic voltage comparator with an input signal dependent power down technique for low power applications is presented here. Without affecting the resolution, a preamplifier stage has been removed from the proposed dynamic voltage comparator in order to reduce the power consumption and its delay. In this design, an input signal dependent power-down technique is used. The proposed design consists of NMOS & PMOS Input Stage Dynamic Voltage Comparator with power down (NISDVC_PD & PISDVC_PD) along with multiplexers for full rail-to-rail input swing. One out of PISDVC_PD and NISDVC_PD is active at a time to reduce power consumption. The proposed comparator has been designed using SCL 180 nm CMOS technology at 1.8 V. The simulation results of the proposed design show that the power consumption and delay is 94.1 µW and 208.28 ps at 500 MHz whereas at 2 GHz the value of the power consumption and delay is 147.7 µW and 212.5 ps, respectively. Furthermore, the offset voltage is obtained as 185.3 µV and the sensitivity of the circuit is 0.15 µV.

Directional solidification of a TiAl alloy by combined Bridgman and power-down technique

Directional solidification of a TiAl alloy by combined Bridgman and power-down technique

Columnar to Equiaxed Transition in Peritectic TiAl Based Alloy Studied by a Power-Down Technique

Columnar to equiaxed transition (CET) was studied in a peritectic TiAl-based alloy with chemical composition Ti-45.1Al-4.9Nb-0.25C-0.2B (at.%). Solidification experiments were conducted in a Bridgman-type apparatus using cylindrical moulds made of high-purity Y2O3. The methodology containing appropriate etching and observations under flat light in stereo-microscope was used to identify the morphology of primary β phase grains and position of CET in the samples˰ All samples prepared by power down-technique showed sharp CET. The position of the CET measured from the beginning of the sample depends on the applied cooling rate and increases from approximately 65 to 115 mm by decreasing cooling rate from 50 to 15 K/min. Based on terrestrial experiments, the future work focused on microgravity and hypergravity CET experiments and numerical modeling is proposed. A Bridgman furnace front tracking method will be applied in future work to complement the experimental results here as part of the European Space Agency GRADECET programme. This modeling will input directly into planned microgravity and hypergravity CET experiments.

Tailored microstructure creation of TiAl-based refractory alloys within VGF solidification

The work is aimed at the study of the formation and refinement of primary microstructure appearing in the refractory lightweight structural TiAl-based intermetallics during their solidification from the melt. The alloy with Ti–46Al–8Nb (at.%) nominal composition is selected for applied study in microstructure engineering. For tailored microstructure development, the Directional Solidification (DS) of pre-synthesized alloy was performed in the vertical multizone electro-furnace by Vertical Gradient Freezing (VGF) power-down technique in pure argon environment. Both columnar-dendrite, and equiaxed-granular reproducible as-cast microstructures have been produced in DS ingots, basing onto Columnar-to-Equiaxed Transition (CET) diagram exploration. Particular attention was paid further to equiaxed microstructure improvement by combination of modifying doping of alloy with boron grain refiner and VGF processing. As a result the perfect inoculated microstructure of Ti–44Al–7Nb–2B (at.%) ingots was produced with 120 μm mean grain diameter, low scattering of dimensional characteristics and high tolerance to DS process parameters variation. DS samples were examined by SEM microanalysis along with EBSD and Auger spectrometry of boride particles in the alloy matrix. The nature, state and exact composition of precipitated borides are discussed along with the nucleation mechanism in relation to the literature data.

On the state of boride precipitates in grain refined TiAl-based alloys with high Nb content

Abstract The work is aimed at the refinement of primary microstructure appearing in the refractory lightweight structural TiAl-based intermetallics during their solidification from the melt. The green alloy with Ti–46Al–8Nb (at.%) nominal composition is selected for applied study in microstructure engineering. For grain refining, the metallurgical alloying of the material was performed with microcrystalline titanium diboride TiB2 additive, along with subsequent Directional Solidification (DS) in the vertical multizone electro-furnace by power-down technique in pure argon environment. As a result the uniform equiaxed microstructure of Ti–44Al–7Nb–2B (at.%) ingots was produced with low dimensional scattering and characteristic grain diameter of 110–130 μm. DS samples were examined by SEM microanalysis along with EBSD and Auger spectrometry of boride particles in the alloy matrix. It was stated that initial diboride TiB2 additive was completely dissolved and has been afterwards re-precipitated in the course of DS into orthorhombic (Ti,Nb)B monoboride single-crystalline micro-particles of B27 structure, acting as randomly distributed point seeds for inoculated solid grains nucleation. The nature, exact composition and nucleation potency of newly formed borides are discussed along with the nucleation mechanism in relation to the literature data. The addition of trace amount (below 0.1 at.%) of beryllium solute is proposed for the enhancement of β-grain refinement at solidification stage.

Microstructure engineering of TiAl-based refractory intermetallics within power-down directional solidification process

Abstract The work is aimed at the study of the formation and refinement of primary microstructure appearing in the refractory lightweight structural TiAl-based alloy of Ti–46Al–8Nb (at.%) nominal composition. For tailored microstructure development, the Directional Solidification (DS) of pre-synthesized alloy was performed in the vertical multizone resistive electro-furnace by power-down technique in pure argon environment. Both columnar-dendrite, and equiaxed-granular reproducible as-cast microstructures have been produced in DS ingots, basing on Columnar-to-Equiaxed Transition (CET) diagram and experimental exploration. Particular attention was paid further to equiaxed microstructure improvement by combination of modifying doping of alloy with boron grain refiner and DS processing. As a result the perfect inoculated microstructure of Ti–44Al–7Nb–2B (at.%) ingots was produced with 100 μm mean grain diameter, low scattering of dimensional grain characteristics and high tolerance to DS process parameters variation.

Thermal Management of On-Chip Caches Through Power Density Minimization

Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can be suboptimal when thermal effects are considered. Then, we propose a thermal-aware cache power-down technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which then exponentially reduces the leakage. Thus, leakage power of the active parts is reduced in addition to the power eliminated from the parts that are turned off. Simulations based on SPEC2000, NetBench, and MediaBench applications in a 70-nm technology show that the proposed thermal-aware architecture can reduce the total energy consumption by 53% compared to a conventional cache, and 14% compared to a cache architecture with thermal-unaware power reduction scheme. Second, we show a block permutation scheme that can be used during the design of the caches to maximize the distance between blocks with consecutive addresses. Because of spatial locality, blocks with consecutive addresses are likely to be accessed within a short time interval. By maximizing the distance between such blocks, we minimize the power density of the hot spots in the cache, and hence reduce the peak temperature. This, in return, results in an average leakage power reduction of 8.7% compared to a conventional cache without affecting the dynamic power and the latency. Overall, both of our architectures add no extra run-time penalty compared to the thermal-unaware power reduction schemes, yet they result in a significant reduction in the total energy consumption of a cache

Investigations on Columnar-to-Equiaxed Transition in Binary Al Alloys with and without Grain Refiners

We have investigated the columnar to equiaxed transition experimentally in directionally solidified hypoeutectic binary AlSi alloys with and without grain refinement particles and for different processing parameters in the framework of the ESA-MAP CETSOL (Columnar-to-equiaxed transition in solidification processing). A power-down technique was used in a Bridgman-Stockbarger type gradient-furnace to simultaneously increase the solidification rate and decrease the temperature gradient in the cylindrical sample during directional solidification vertically upwards. The position of the CET was determined from the cut and polished samples and correlated to the applied cooling rate for different experiments. Critical parameters for the temperature gradient and the solidification rate at the transition were determined from cooling curves measured within the sample and from a time-of-flight analysis of ultrasonic pulses propagated in the solid part of the sample and being reflected at the solid-liquid interface. The critical values found are compared to the deterministic models of Hunt and of Martorano et al. The objective of this contribution is the presentation of preliminary results for the different alloys and processing parameters of ground-based experiments. These results will be used for the testing of different models describing the CET within the framework of the ESA-MAP CETSOL and for the preparation of comparative microgravity experiments.

An 8 ns 256 K BiCMOS RAM

A 256 K word*1 bit emitter-coupled logic (ECL) RAM, which achieves an 8 ns address access time, less than 400 mW power consumption at 50 MHz operation, and 150 mW at standby mode, is presented. To achieve an address access time of less than 10 nss and high packing density, an advanced 1.0 mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is used. A 9 GHz bipolar transistor cutoff frequency, 0.26 ns ECL gate propagation delay time, and 0.35 ns BiCMOS gate have been obtained. A 1.0 mu m design rule permits layout of an NMOS memory cell with a high-resistance polysilicon load in 54.7 mu m/sup 2/ and a 4.09*8.60 mm/sup 2/ chip. High performance is achieved by an optimized circuit design using a new input buffer, a BiCMOS decoder, and a high-speed bipolar sense amplifier. An active pull-down emitter-follower circuit and a BiCMOS current mirror ECL-MOS level shift circuit improve input buffer delay to less than 1.8 ns. A power-down technique has been studied to reduce standby power. Some experimental results are presented. High-speed address access is observed over a wide operational range. >