Interconnect Power Dissipation Research Articles

Reconfigurable data encoding schemes for on-chip interconnect power reduction in deep submicron technology

With technology scaling, size of both transistor and interconnects are reduced. Power dissipation due to dynamic switching is high in the interconnects. Suitable encoding schemes that reduces transition between data bits are used to minimize interconnect power dissipation. In this paper transition between data bits is minimized based on three novel data encoding schemes identifying the novel methods estimates bit transitions in a pair of data bits and performs half inversion or full inversion on one byte of data thus reducing the switching activity by 50%. The encoder and decoder for the three encoding schemes are modelled in verilog hardware description language (HDL) and implemented using application specefic integrates circuit (ASIC) flow targeting 32 nm. Technology over all power dissipation of encoding scheme is 1.04 μW in addition over head area of 210 cells with encoding delay of 340 ps. Encoder decoder register transfer logic (RTL) code is implemented and the total area required is 34980 units. The data encoding and decoding schemes are suitable for low power applications.

An Adaptive and High Coding Rate Soft Error Correction Method in Network-on-Chips

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reducedas the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.Keywords
 Error Correction Code, Fault-Tolerance, Network-on-Chip.
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Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration (VLSI) circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

Optical and Electrical Properties of ECR-PECVD Grown SiCN Thin Films

Recent progress in scaling down the metal-oxide semiconductor (MOS) devices accompanied limitations arising from quantum effects, which leads to a search for new materials. Silicon oxide (SiO2) thin films have been a favourable dielectric for more than 4 decades. Their usage have become impractical due to the power dissipation and delay in interconnects. To increase the electrical performance, low extinction coefficient (low-k) dielectric materials are being developed as a substitute to SiO2. Those materials draw considerable attraction due to their advances in the integrated circuit technology to increase the transistor density. Among numerous materials, silicon carbonitride (SiCN), which is an intermediate compound between silicon nitride (SiN) and silicon carbide (SiC), has become noteworthy with its unique properties as low-k, robustness, high thermal stability, and wide bandgap of 2.2eV- 5eV1. In this work we present the optical, structural, and electrical analysis of SiCN thin films grown using electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The influence of the precursors (SiH4, C2H2, and N2 gases) on the composition and electronic structure of thin films which were characterized by Rutherford backscattering spectroscopy (RBS) and Fourier transmission infrared spectroscopy (FTIR). Furthermore, current-voltage characteristics were studied in dark and illuminated environment at room temperature. We studied the variation of photodiode characteristics with the thin film compositions. These results were also compared with the SiCN thin films growth using identical parameters except for the carbon source (CH4 gas) which has been reported in earlier studies2. Our findings showed that the hydrogen content influenced the optical coefficients of these two set of samples. Index of refraction and extinction coefficients were characterized by variable angle spectroscopic ellipsometry (VASE). In addition to our works on developing low-k matrix to enhance the performance of the integrated circuits, the wide gap feature of SiCN thin films enable us to consider the ultraviolet (UV) photo responsivity effect which is studied for photodetector device application.

A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects

Multiwall carbon nanotube (MWCNT) has been investigated as a potential interconnect material for future advanced technology nodes. The present paper analyzes performance of MWCNT interconnects using current mode signaling (CMS) scheme. The novelty of the present work can be stated as: Firstly, a unified model is proposed for both copper and MWCNT interconnects using finite-difference time-domain (FDTD) technique. Secondly, this model is applicable for both the conventional voltage mode signaling and more versatile CMS schemes. Furthermore, the presented FDTD-based model is valid for single as well as M-line coupled interconnects in integrated circuits. The model also incorporates CMOS gate as driver for MWCNT interconnect. Thirdly, power model using FDTD technique is investigated for the first time. Accurate formulation and computation of power dissipation in CMS MWCNT interconnects are presented in the paper. Propagation delay, power dissipation and power_delay_product (PDP) are the performance metrics considered for single-line CMS MWCNT interconnect. Crosstalk is analyzed for 2-Line and 5-Line coupled interconnects. It is investigated that CMS scheme leads to about 4 times lesser propagation delay and 2.5 times reduced PDP in MWCNT interconnect than the conventional copper interconnect for interconnect length of 4500 $$\upmu $$ m. The technology node considered is 32 nm. The response of the system is accurately computed using the proposed FDTD-based model. The maximum percentage error between results obtained by the proposed analytical model and SPICE simulation model is <3% for the various test cases.

An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts

We propose a grid-graph algorithm for interconnect routing and buffer insertion in nanometer VLSI layout designs. The algorithm is designed to handle multiconstraint optimizations, namely timing performance and power dissipation. The proposed algorithm is called HRTB-LA, which stands for hybrid routing tree and buffer insertion with look-ahead. In recent VLSI designs, interconnect delay has become a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. However, the buffer itself consumes power and it has been shown that power dissipation overhead due to buffer insertions is significantly high. Many methodologies to optimize timing performance with power constraint have been proposed, and no algorithm is based on dynamic programing technique using a grid graph. In addition, most of the algorithms for buffer insertion use a postrouting buffer insertion approach. In the presence of buffer obstacles, these postrouting algorithms may produce poor solutions. On the other hand, the simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP complete. Hence, our main contribution is an efficient algorithm using a hybrid approach for multiconstraint optimization for multisink nets. The algorithm uses dynamic programming to compute incrementally the interconnect delay and power dissipation of the inserted buffers while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multiconstraint optimizations and produces a solution up to 30% better compared to a postrouting buffer insertion algorithm in comparable runtime.

Investigation and improvement of the dispenser printing of electrical interconnections for smart fabric applications

Electrical interconnections are essential for the integration of electronic functions in a fabric. These interconnects can be dispenser printed on a fabric; however printing directly on a breathable woven fabric surface is challenging due to the high surface variation and porosity defined by the weave. This paper, for the first time, experimentally shows that fabric surface variation leads to inconsistent printed structures which adversely affects the electrical properties of printed conductive tracks. It investigates a solution of overcoming the fabric surface variation in the form of dispenser printing an interface layer between the conductive ink and the fabric surface. Four dielectric inks DuPont 5018, Electra EFV4/4965, Fabinks-UV-IF-1004 and Fabinks-UV-TC0233 are quantitatively evaluated, as interface materials, in terms of surface consistency, thickness consistency, repeatability, flexibility, thermal stability and the electrical characteristics of conductive tracks printed on them. All four of the evaluated interface materials significantly reduced the fabric surface variation by more than 95% and provided a suitable low variation surface for printing subsequent electronic layers. Conductive tracks, dispenser printed on the four interface materials, produced ∼90% lower electrical resistivity compared to tracks printed directly on the fabric and similar resistivity to dispenser printed tracks on Kapton, a traditional printed electronic substrate. An increased focus on low powered electronics especially for wearables requires the electrical interconnections to dissipate minimum power. The innovative interface layer approach allows fabrication of low resistance electrical interconnections on fabric substrates reducing interconnect power dissipation, making this approach highly suitable for smart fabric applications. Reported details of dispenser printing of interface materials can be used for replicating these results on a range of fabric substrates. The paper also reports a novel thermal imaging based method of analysing resistance distribution within a printed conductive track to assess the geometrical consistency of printed electrical interconnections.

Bus encoder design for crosstalk and power reduction in RLC modelled VLSI interconnects

Purpose – This paper aims to reduce the worst-case crosstalk effects for resistance, inductance and capacitance (RLC) interconnects using the bus encoding technique. In current nanoscale technology, power dissipation, propagation delay and crosstalk performance of interconnects determine the overall performance of a chip. Signal integrity issues due to crosstalk in the form of voltage glitches, overshoots, undershoots, undesirable noise, propagation speed ups and downs, etc. are some of the major deterrents for high-performance RLC modelled (VLSI) interconnects. This research paper primarily proposes two novel encoding methods (I and II) for RLC modelled interconnects to reduce the effect of crosstalk, simultaneous switching noise (SSN) and power consumption. Design/methodology/approach – The proposed methods are based on the bus encoding method that is effective and well-suited for the reduction of the crosstalk noise. This method encodes or transforms incoming data in a manner that encoded data contain minimum or no crosstalk effects. The proposed encoding method uses the bus invert (BI) method. The proposed encoding methods are able to avoid the worst-case crosstalks while consuming lesser power during transmission in VLSI interconnects. Findings – It is observed that the proposed encoders reduced/eliminated the worst-case crosstalk by reducing SSN. The encoding method I also reduces Type 0 crosstalk by 100 per cent, while Type 1 crosstalk is reduced by 36.4 per cent and Type 2 is reduced by 16.8 per cent. The average simultaneous switching is reduced by 51.1 per cent. Similarly, encoding method II reduces switching activity by 10.3 per cent, whereas the coupling activity is reduced by 35.4 per cent. Furthermore, encoding method II also reduced Type 0, Type 1 and Type 2 crosstalk by 100, 36.9 and 27.1 per cent, respectively. Hence, the proposed encoding methods reduced the worst-case crosstalk completely. Research limitations/implications – In VLSI technology, the reduction in feature size and the increase in operating frequency are quite rapid. This leads to higher propagation delay, crosstalk and power dissipation through the interconnects. Most of the previously proposed encoders/decoders have turned out to be unsuitable for RLC modelled interconnects. Hence, the proposed encoder would be extremely useful for crosstalk reduction in newer operating conditions. Practical implications – The encoding method I identifies the harsh crosstalks, that is Type 0 and Type 1, in the inverted and non-inverted forms of incoming data with respect to the previous data. The data having minimum crosstalk in the inverted and non-inverted forms are only sent through the transmission line. The encoding method I also removes the worst-case crosstalk and simultaneously reduces other mild crosstalks. The removal of worst-case crosstalk improves the overall performance of the interconnect. The encoding method II identifies Type 2 crosstalk along with Type 0 and Type 1 similar to encoding method I. Furthermore, the encoding method II exhibits an improvement over method I in terms of reduction in crosstalk and power dissipation. Originality/value – This paper proposes a novel encoding method to reduce worst-case crosstalk effects that reduces SSN. The proposed encoding methods achieve their purpose of crosstalk reduction for several technology nodes.

Bufferless Routing in Optical Gaussian Macrochip Interconnect

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within ${{N}}$ hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems.

A PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTING

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.

Control of tube parameters on SWCNT bundle interconnect delay and power dissipation

Purpose – This paper aims to propose to study the control of tube parameters in terms of diameter, separation between adjacent tubes and length, on delay and power dissipation in single-walled carbon nanotube (SWCNT) bundle interconnect for VLSI circuits. Design/methodology/approach – The paper considers a distributed-RLC model of interconnect. A CMOS-inverter driving a distributed-RLC model of interconnect with load of 1 pF. A 0.1 GHz pulse of 2 ns rise time provides input to the CMOS-inverter. For SPICE simulation, predictive technology model (PTM) is used for the CMOS-driver. The performance of this setup is studied by SPICE simulation in 22 nm technology node. The results are compared with those of currently used copper interconnect. Findings – SPICE simulation results reveal that delay increases with increase in separation between tubes and diameter whereas the reverse is true for power dissipation. The authors also find that SWCNT bundle interconnects are of lower delay than copper interconnect at various lengths and higher power dissipation due to dominance of larger capacitance of tube bundle. Originality/value – The investigations show that tube parameters can control delay and this can also be utilized to decrease power dissipation in SWCNT bundle interconnects for VLSI applications.

Influence of distance between adjacent tubes on SWCNT bundle interconnect delay and power dissipation

Influence of separation between adjacent tubes of various lengths and tube diameters, on delay and power dissipation in single walled carbon nanotube (SWCNT) bundle interconnect has been analyzed. The results are compared with those of currently used copper interconnects at 22nm technology node. SPICE simulation results reveal that delay increases with an increase in the separation between adjacent tubes for the entire range of length values and tube diameters whereas the reverse is true for power dissipation.

Effect of Equal and Mismatched Signal Transition Time on Power Dissipation in Global VLSI Interconnects

Effect of Equal and Mismatched Signal Transition Time on Power Dissipation in Global VLSI Interconnects

Exploring Asynchronous MMC-Based Parallel SA Schemes for Multiobjective Cell Placement on a Cluster of Workstations

Combinatorial optimization problems are generally NP hard problems that require large run-times when solved using iterative heuristics. Parallelization using distributed or shared memory computing clusters thus becomes a natural choice to speed up the execution times of such problems. In this paper, several parallel schemes based on an asynchronous multiple-Markov-chain (AMMC) model are explored to parallelize simulated annealing (SA), used for solving a multiobjective VLSI cell placement problem. The different parallel schemes are investigated based on the speedups and solution qualities achieved on an inexpensive cluster of workstations. The problem requires the optimization of conflicting objectives (interconnect wire-length, power dissipation, and timing performance), and fuzzy logic is used to integrate the costs of these objectives. The goal is to develop effective AMMC-based parallel SA schemes to achieve near linear speedups while maintaining or achieving higher solution qualities in less time and to analyze these parallel schemes against the common critical performance factors.

Trends in Emerging On-Chip Interconnect Technologies

In deep submicron (DSM) VLSI technologies, it is becoming increasingly harder for a copper based electrical interconnect fabric to satisfy the multiple design requirements of delay, power, bandwidth, and delay uncertainty. This is because electrical interconnects are becoming increasingly susceptible to parasitic resistance and capacitance with shrinking process technology and rising clock frequencies, which poses serious challenges for interconnect delay, power dissipation and reliability. On-chip communication architectures such as buses and networks-on-chip (NoC) that are used to enable inter-component communication in multi-processor systems-on-chip (MPSoC) designs rely on these electrical interconnects at the physical level, and are consequently faced with the entire gamut of challenges and drawbacks that plague copper-based electrical interconnects. To overcome the limitations of traditional copper-based electrical interconnects, several research efforts have begun looking at novel interconnect alternatives, such as on-chip optical interconnects, wireless interconnects and carbon nanotube-based interconnects. This paper presents an overview and current state of research for these three promising interconnect technologies. We also discuss the existing challenges for each of these technologies that remain to be resolved before they can be adopted as replacements for copper-based electrical interconnects in the future.

Characterization of Chemical Bonding in Low-K Dielectric Materials for Interconnect Isolation: A XAS and EELS Study

AbstractThe use of low dielectric constant materials in the on-chip interconnect process reduces interconnect delay, power dissipation and crosstalk noise. To achieve the requirements of the ITRS for 2007-2009 minimal sidewall damage from etch, ash or cleans is required. In chemical vapor deposited (CVD) organo-silicate glass (OSG) which are used as intermetal dielectric (IMD) materials the substitution of oxygen in SiO2 by methyl groups (-CH3) reduces the permit-tivity significantly (from 4.0 in SiO2 to 2.6-3.3 in the OSG), since the electronic polarizability is lower for Si-C bonds than for Si-O bonds.However, plasma processing for resist stripping, trench etching and post-etch cleaning removes C and H containing molecular groups from the near-surface layer of OSG. Therefore, compositional analysis and chemical bonding characterization of structured IMD films with nanometer resolution is necessary for process optimization.OSG thin films as-deposited and after plasma treatment are studied using X-ray absorp-tion spectroscopy (XAS) and electron energy loss spectroscopy (EELS). In both techniques, the fine structure near the C1s absorption or energy loss edge, respectively, allows to identify C-H, C-C, and C-O bonds. This gives the opportunity to differentiate between individual low-k mate-rials and their modifications. The O1s signal is less selective to individual bonds. XAS spectra have been recorded for non-patterned films and EELS spectra for patterned structures. The chemical bonding is compared for as-deposited and plasma-treated low-k materials. The Fluo-rescence Yield (FY) and the Total Electron Yield (TEY) recorded while XAS measurement are compared. Examination of the C 1s near-edge structures reveal a modified bonding of the re-maining C atoms in the plasma-treated sample regions.

Minimizing Power Dissipation in Optical Interconnects at Low Voltage Using Optimal Modulator Design

A strong motivation for insertion of optical interconnects in short-distance applications such as chip-to-chip or back-plane communication, apart from high bit rates, is their potential to achieve these bit rates at low power compared to the currently prevalent copper based interconnects. Thus, it is imperative to construct design methodologies which minimize the total optical link power dissipation. We present one such methodology, where we optimize the quantum-well modulators to minimize the power dissipation in modulator-based optical interconnects. In the first part of the paper, the focus is on obtaining the optimal modulator metrics [contrast ration (CR) and insertion loss], which yield the lowest total power (receiver and the modulator). The trends are studied as a function of the input laser power and bit rate. Having obtained the desirable modulator metrics and the corresponding power dissipation, in the second part, the focus is on the feasibility of these metrics in the light of voltage swing constraints. The biggest concern with the modulator based optical link is the low CR, especially at low voltage swing. While studying these concerns, we also provide insight into the physical design of the modulator including, its intrinsic region thickness, pre-bias voltage, and the size and the number of quantum-wells. Specifically, we outline the method to obtain the design parameters, which allows minimum power dissipation with the least laser power. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.

A power-optimal repeater insertion methodology for global interconnects in nanometer designs

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.

Dynamic current mode logic (DyCML): a new low-power high-performance logic style

This paper introduces a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike CML circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. A 16-bit DyCML carry look-ahead adder (CLA), fabricated in 0.6-/spl mu/m CMOS technology, attains a delay of 1.24 ns and dissipates 19.2 mW at 400 MHz.

Fluorinated amorphous carbon films for low permittivity interlevel dielectrics

The need to substitute SiO2 with low dielectric constant (κ) materials increases with each complementary metal–oxide–semiconductor process generation as interconnect RC delay, crosstalk, and power dissipation play an ever larger role in high-performance integrated circuits. Fluorinated amorphous carbon films (a-C:F,H) with low-κ properties (κ∼2.0–2.4) deposited by plasma-assisted chemical vapor deposition (CVD) techniques provide several advantages including low temperature processing, good gap fill capabilities, minimal moisture absorption, and simple implementation. Several deposition techniques have been examined, including high-density plasma and parallel-plate plasma-assisted CVD. In each case, it is possible to deposit a-C:F,H films with widely varying properties, such as κ and thermal stability. This has led to a good deal of confusion as to what is required to produce useful material. Results from many different sources are examined to develop a coherent picture of the relationships between deposition techniques, microstructural features, and macroscopic properties, and to summarize the scientific and technical challenges that remain for a-C:F,H implementation. The relationships between film deposition parameters such as applied substrate bias and film properties are presented in the discussion. In addition, x-ray photoelectron spectroscopy and network constraint theory are used to develop connections between microstructural and macroscopic properties, as well as to show how deposition parameters can be used to create a predictive model. This will demonstrate what process parameters are important in film formation. Finally, efforts to incorporate this material into integrated circuits, as well as measurements of the reliability and performance will be reviewed.