Power Cycling Stress Research Articles

Predicting Lifetime of Semiconductor Power Devices Under Power Cycling Stress Using Artificial Neural Network

This paper analyzes the problem of modeling the lifetime in semiconductor power devices subjected to power cycling stress using Artificial Neural Networks (ANNs). The paper discusses the optimal configuration of ANNs for the considered problem, aiming at minimizing the error in the predicted lifetime and at reducing the required number of training data. Moreover, being the device lifetime a stochastic parameter, the suitability of ANNs is verified in the case of variability in the input training data. Power cycling tests are conducted on IGBT devices and experimental number of cycles to failure are adopted for the training process of the ANN.

Competitive Failures Decoupling and Mechanisms Analysis of SiC MOSFET Module Under Power Cycling Stress

Competitive Failures Decoupling and Mechanisms Analysis of SiC MOSFET Module Under Power Cycling Stress

Reliability of SiC MOSFET Power Modules under Consecutive H3TRB and Power Cycling Stress

Power semiconductor modules are subject to both thermo-mechanical stress and electro-chemical stress during field operation. Usually, those stressors are investigated separately and possible interaction of both degradation mechanisms is neglected. In this work, the effect of combined thermo-mechanical and electro-chemical stress is investigated by means of consecutive H3TRB and PCT testing. One test group had been subjected to power cycling before the H3TRB test was performed, while another test group had been exposed to H3TRB stress before the power cycling test. As a reference, devices without preconditioning were tested in both, H3TRB and power cycling and are also used to compare the H3TRB and power cycling performance of the SiC devices to similar silicon devices. The results show, that the SiC devices feature a significantly better H3TRB performance than comparable silicon devices, but are inferior in terms of power cycling performance. Furthermore, the results for both test groups of the combined tests indicate that the failure modes for the previously stressed devices were the same as for the pristine devices and no impact of either preceding stress on the devices' lifetime could be observed. Therefore, the results of this work suggest no interaction between both stressors, at least not for the devices used for this investigation.

Influence of Power Cycling Test Methodology on the Applicability of the Linear Damage Accumulation Rule for the Lifetime Estimation in Power Devices

The lifetime of power semiconductor devices, operating under a given mission profile and subjected to power cycling stress, is conventionally estimated under the assumption of linear damage accumulation rule, that is the application of the Miner's rule. To this purpose, lifetime models must be properly defined allowing to take into account for the relevant parameters of power cycling stress. This work shows how to estimate a cumulative distribution function in the case of an arbitrary temperature swing profile, starting from the statistical distribution at constant power cycling conditions. It is found that the accuracy of the linear damage accumulation rule is related to the experimental methodology adopted for power cycling tests. A detailed experimental activity is carried out on packaged IGBT devices, providing useful guidelines for the definition of lifetime models to be adopted in the Miner's rule.

Degradation mechanism analysis for SiC power MOSFETs under repetitive power cycling stress

In this work, investigation on the degradation behavior of 1.2 kV/52 A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress has been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms have also been analyzed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the x-ray inspection system, scanning acoustic microscope, scanning electron microscope, emission microscope, etc. Experimental results reveal that both the degradation of the gate oxide on the chip-level and the degradation of the bond wire and solder layer on the package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (V th) and gate leakage current (I gss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electrons on the chip-level, while the appearance of fatigue in the bond wire and the delamination of the solder layer imply the degradation on the package-level. This work may provide some practical guidelines for assessments of the reliability of SiC power MOSFETs in power conversion systems.

Degradation Behavior and Defect Analysis for SiC Power MOSFETs Based on Low-Frequency Noise Under Repetitive Power-Cycling Stress

In this article, the degradation behavior of the commercial 1.2-kV SiC power MOSFETs was investigated under repetitive power-cycling stress, and defect analysis based on low-frequency noise (LFN) was carried out. The experimental results show that increasing power-cycling stress results in a forward shift of threshold voltage and increasing ON-resistance. Meanwhile, the drain-to-source current significantly decreases with the increase of the cycles. Furthermore, the gate–source leakage current of the device became larger and the blocking characteristics deteriorated after 10-k cycles. The negative shift of the gate-capacitance versus gate-voltage curve was analyzed. Trap characterization was performed by using the LFN method, and it was found that the trap density of the device increased 5.47 times after 10-k cycles. The physical mechanism could be attributed to electrically active trapped charges generated at the SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface during power-cycling stress. This article may be helpful for degradation detection and fault analysis of SiC power MOSFETs in the electronic system.

“Limiting power cycling stress in power MOSFETs by active thermal control”

In this work we propose a system which is able to actively control the temperature of a power MOSFET, in order to limit the temperature swing and hence to reduce the power/thermal cycling effect. To this purpose a dedicated driving circuit, allowing to control the gate voltage of the switching device under investigation, is used in a synchronous buck converter. Therefore, power losses can be modulated in order to reach the desired temperature through self-heating effects. The implemented control system is able to compensate the non-linear relationship between the gate voltage and the on-resistance. Moreover, to improve the response of the system, a predictor has been implemented, having the capability of on-line tuning the thermal resistance of the device. Experimental results are reported to demonstrate the suitability of this solution to control the temperature in the semiconductor device. The reduction of temperature swing under power and thermal cycling is also demonstrated.

Review and analysis of SiC MOSFETs’ ruggedness and reliability

SiC MOSFETs (silicon carbide metal-oxide semiconductor field-effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety-critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in-depth analysis. The ruggedness of SiC MOSFETs discussed here includes short-circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high-temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

Degradation in electrothermal characteristics of 4H-SiC junction barrier Schottky diodes under high temperature power cycling stress

The electrothermal characteristics and degradation mechanism of 4H-SiC JBS under high temperature power cycling (HTPC) stress were investigated based on thermal structure function, failure analysis and electrothermal simulation. Results show that, the HTPC stress at different temperature conditions (maximum junction temperature Tjmax = 150 °C and Tjmax = 200 °C) have different effects on the reverse breakdown voltage (Vbr), reverse leakage current and the on-resistance (Ron-sp). It was that the increased reverse leakage currents with HTPC stress are due to the Schottky barrier lowering at the beginning. However, as the heat concentration effect increased at the metal/4H-SiC interface, the contribution of tunneling to leakage current is the major components. So the heat flux path and thermal distribution are very crucial to the reliability of chip and package. It can be concluded that the degradations of die-attach, die surface and metal/SiC interface are the main reliability limiting factors of SiC JBS diodes under high temperature applications.

Power cycling fatigue and lifetime prediction of power electronic devices in space applications

This paper presents a complete study about power cycling stress on space components. Power cycling fatigue is generally studied for traction or automotive applications. But power cycling failures are also a major cause of concern in space industry. In this paper we successively address the following subjects: definition of the power cycling stress in space applications, experimental power cycling test on space components and lifetime prediction for a typical earth observation application.

On the effect of power cycling stress on IGBT modules

IGBT reliability is becoming of great relevance, due to the range of application of these devices. Nevertheless, no standard test methods have been established, in order to evaluate their power cycling reliability. On this paper we report on the effect of ΔT and T jmaz on the power cycling capability of IGBT dice, by means of a matrix of stress cycles with different values of ΔT and T jmax . Failure analysis has been performed, in order to understand the failure mechanisms induced by the stress.