Technique For Reducing Power Consumption Research Articles

10 GHz inverter‐type‐time‐amplifier based phase noise filter with −133 dBc/Hz phase noise sensitivity

This Letter presents an inverter-type time amplifier (TA)-based phase noise filter (TAPNF) with 8 dB phase noise suppression and −133 dBc/Hz phase noise sensitivity at 1 MHz offset. The phase noise improvement strategy, low noise TA design and power consumption reduction techniques are presented. The TAPNF is fabricated in a 65 nm CMOS process with 1.4 mm × 1.6 mm chip area and consumes 50 mW power. To authors’ best knowledge, the TAPNF achieves the best phase noise and figure-of-merit compared with state-of-the-arts with similar technologies and carrier frequencies.

Open SystemC Simulator with Support for Power Gating Design

Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator.

Power saving in regular interconnection networks

The high level of computing power required for some applications can only be achieved by multiprocessor systems. These systems consist of several processors that communicate by means of an interconnection network. The huge increase both in size and complexity of high-end multiprocessor systems has triggered up their power consumption. Complex cooling systems are needed, which, in turn, increases power consumption. Power consumption reduction techniques are being applied everywhere in computer systems and the interconnection network is not an exception, as its contribution is not negligible. In this paper, we propose a mechanism to reduce interconnect power consumption that combines two alternative techniques: (i) dynamically switching on and off network links as a function of traffic (any link can be switched off, provided that network connectivity is guaranteed), (ii) dynamically reducing the available network bandwidth when traffic becomes low. In both cases, the topology of the network is not modified. Therefore, the same routing algorithm can be used regardless of the power saving actions taken, thus simplifying router design. Our simulation results show that the network power consumption can be greatly reduced, at the expense of some increase in latency. However, the achieved power reduction is always higher than the latency penalty.