Power Consumption Of Multicore Processor Research Articles

Imitation Learning-Based Performance-Power Trade-Off Uncore Frequency Scaling Policy for Multicore System.

As the importance of uncore components, such as shared cache slices and memory controllers, increases in processor architecture, the percentage of uncore power consumption in the overall power consumption of multicore processors rises significantly. To maximize the power efficiency of a multicore processor system, we investigate the uncore frequency scaling (UFS) policy and propose a novel imitation learning-based uncore frequency control policy. This policy performs online learning based on the DAgger algorithm and converts the annotation cost of online aggregation data into fine-tuning of the expert model. This design optimizes the online learning efficiency and improves the generality of the UFS policy on unseen loads. On the other hand, we shift our policy optimization target to Performance Per Watt (PPW), i.e., the power efficiency of the processor, to avoid saving a percentage of power while losing a larger percentage of performance. The experimental results show that our proposed policy outperforms the current advanced UFS policy in the benchmark test sequence of SPEC CPU2017. Our policy has a maximum improvement of about 10% relative to the performance-first policies. In the unseen processor load, the tuning decision made by our policy after collecting 50 aggregation data can maintain the processor stably near the optimal power efficiency state.

Tight Lower bound on power consumption for scheduling real-time periodic tasks in core-level DVFS systems

Dynamic voltage and frequency scaling (DVFS) is a widely used solution to reduce power consumption. Modern multi-core architectures support core-level DVFS, where each core has its own power supply and can change its frequency independently from other cores. This paper aims at optimizing power consumption of multi-core processors while ensuring deadline constraints of real-time periodic tasks. From theoretical aspects, we prove a tight lower bound of power consumption for executing real-time tasks, which indicates to what extent scheduling algorithms can approach. From practical aspects, we propose a Power Scaling Algorithm (PSA) to assign real-time periodic tasks to a power efficient platform. PSA not only determines the optimal frequencies for each core, but also provides the appropriate number of active cores, which can skip the local optimum and achieve the global minimum. This lower power bound is validated by several extensive experiments.

A Cost-Effective Hardware Approach for Measuring Power Consumption of Modern Multi-Core Processors

Multiple processor cores are built within a chip by advanced VLSI technology. With the decreasing prices, multi-core processors are widely deployed in both server and desktop systems. The workload of multi-threaded applications could be separated to different cores by multiple threads, such that application threads can run concurrently to maximize overall execution speed of the applications. Moreover, for the green trend of computing nowadays, most of modern multi-core processors have a functionality of dynamic frequency turning. The power-level tuning techniques are based on Dynamic Voltage and Frequency Scaling (DVFS). In order to evaluate the performance of various power-saving approaches, an appropriate technique to measure the power consumption of multi-core processors is important. However, most of approaches estimate CPU power consumption only from CMOS power consumption data and CPU frequency. These approaches only estimate the dynamic power consumption of multi-core processors, the static power consumption is not be included. In this study, a hardware approach for the power consumption measurement of multi-core processors is proposed. Thus the power consumption of a CPU could be measured precisely, and the performance of CPU power-saving approaches can be evaluated well.