Power-constrained Simultaneous Noise And Input Matching Research Articles

A Differential Cascode Low Noise Amplifier Based on a Positive Feedback Gain Enhancement Technique

This paper presents a differential low noise amplifier (LNA) based on a new configuration suitable for low-power and low noise applications. By inserting additional positive feedback capacitor connected to drain and source terminal of the cascode transistor, this proposed configuration increases voltage gain because of decreasing the total transconductance by a factor generated a negative conductance. In addition, the differential structure and power-constrained simultaneous noise and input matching (PCSNIM) technique are chosen simultaneously to perform the input matching and to improve the noise figure at the desired band. Using TSMC 0.18μmRF CMOS process, the proposed LNA exhibit a state of the art performance consuming only 7.58 mW from a 1.8 V power supply. Input and output return loss of the LNA are below than −13dB while achieves a power gain of 18.66 dB and a noise figure of 2.03 dB at the band of interest.

Design and Analysis of Monolithic Inductively-Degenerated Cascode Based Low Noise Amplifiers

This paper is on the design and analysis of the five types of inductively-degenerated cascode LNA topologies. The topologies are Simultaneous Noise and Input Matching (SNIM), Power-constrained Simultaneous Noise and Input Matching (PCSNIM), Current-reuse (CR), Folded-cascode (FC) and PCSNIM with output buffer. For each topology, the functionality and design are discussed. Equations are given to enable better understanding on how the circuits perform. The characteristics that distinguish one topology from the others are highlighted. These LNAs were simulated using Silterra’s 0.18 μm CMOS technology and the designs were based on a common current consumption of 4 mA to enable comparative analysis. The results obtained conformed to the theories presented. The performances of the LNAs are within the desired range and in accordance to the W-CDMA requirement.

An Ultra-Low-Power 24 GHz Low-Noise Amplifier Using 0.13 <formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CMOS Technology

This study presents an ultra-low-power 24 GHz low-noise amplifier (LNA) using 0.13 μm CMOS technology. We propose of using the minimum noise measure (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ) as the guideline to determine the optimal bias and geometry of the transistors in the circuit. The power-constrained simultaneous noise and input matching (PCSNIM) technique is also employed for this design. With the proposed design approach, the LNA achieves a peak gain of 9.2 dB and a minimum NF of 3.7 dB under a supply voltage of 1 V. The associated power consumption is only 2.78 mW.

Comments on "CMOS low-noise amplifier design optimization techniques"

The original paper by T.-K. Nguyen et al. (see ibid., vol.52, no.5, p.1433-42, May 2004) analyzes the four low-noise amplifier (LNA) design techniques, i.e.: 1) classical noise matching; 2) simultaneous noise and input matching (SNIM); 3) power-constrained noise optimization; and 4) power-constrained simultaneous noise and input matching (PCSNIM) based on the noise parameter expressions so as to provide the guideline for LNA designers. Unfortunately, there are some errors in the derivations of noise parameter expressions for the SNIM, which also applied to the PCSNIM.

CMOS Low-Noise Amplifier Design Optimization Techniques

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.