Power Circuit Configuration Research Articles

Impact of electric circuit configurations on power generation in a photovoltaic and thermoelectric generator hybrid system

Energy harvesting using a thermoelectric generator (TEG) leverages the Seebeck effect to generate electricity from temperature differences. As the demand for electrical energy rises, especially in zero-energy buildings and building conversions, there is an increasing focus on recovering untapped energy sources within buildings. This study aims to analyze the thermal characteristics of a hybrid energy harvester that integrates a TEG with phase change materials (PCM), with the objective of recovering and generating power from wasted sunlight and heat within a building envelope. Additionally, we experimentally investigated the circuit configuration of the TEG to optimize energy harvesting. The experimental results highlighted distinct power generation patterns depending on the TEG's location. To achieve maximum power output, TEGs exhibiting similar power generation patterns should be configured in series to ensure optimal performance. Implementing the maximum power circuit configuration resulted in a 70 % increase in power generation compared to a non-optimized configuration. Moreover, configuring an equal number of TEGs in series yielded a 94.4 % increase in power generation compared to a scenario where all TEGs were connected in series on a single panel.

A Novel Proportional Multi-Resonant Current Controller Strategy for Reduced DC Voltage fed D-STATCOM with Internal LCL Resonance Damping

Abstract This work focuses on a new topology-control-based D-STATCOM solution with reduced DC bus voltage requirement and with an excellent grid side performance. The proposed solution consists of a main inverter and auxiliary inverter along with a transformer and LCL filter network to achieve the required DC bus reduction. A new controller structure with two proportional-multi resonant controller for the converters with only one of the inductors current as a controlled variable ensures the active damping of the LCL resonance. The power circuit configuration assists the controller to generate a difference in the modulation signal due to non-equal gains in two controllers and helps to achieve the resonance damping without capacitor current sensor. Hence, the corresponding capacitor current sensor can be eliminated. The converter operates for any point of common coupling (PCC) loading conditions and the performance of the controller is immune to the grid impedance variation. A detailed stability study is carried out for the proposed controller. The proposed controller can achieve a very fast dynamic response with an excellent stability margin. The proposed solution is verified through simulation studies and through a scaled-down experimental prototype.

Hybrid-Clamping SVPWM Scheme for a Four-Level Open-End Winding Induction Motor Drive

An open-end winding arrangement is fed with two typical 2-level voltage source inverters (VSIs) on either side to accomplish multilevel inversion. Two voltage source modules (VSIs) DC-link voltages are kept at a 2:1 ratio to realize the open-end winding induction motor (OEW-IM) power circuit’s four-level configuration. However, the higher DC-link voltage capacitor overcharges its lower DC-link voltage counterpart in the 4-level power circuit configuration. This article proposes a new hybrid-clamping space vector PWM (SVPWM) approach to prevent overcharging. Based on the sample moment, the suggested SVPWM technique clamps one inverter and switches to another inverter. Additionally, it clamps one of the inverter’s switching phases. The proposed PWM method has been found to reduce switching power loss in contrast to earlier SVPWM methods. The proposed SVPWM scheme for the 4-level OEW-IM drive is tested and verified using an experimental laboratory setup.

An Enhanced Fault-Tolerant and Autoreconfigurable BLDC Motor Drive for Electric Vehicle Applications

Semiconductor switching devices are susceptible to open-circuit (OC) and short-circuit (SC) faults, adversely affecting the reliability of power converters. This article proposes a multiple-switch fault-tolerant and autoreconfigurable brushless direct current (BLDC) motor drive configuration, suitable for electric vehicle applications, owing to its enhanced reliability. The proposed power circuit configuration, along with its fault diagnostic algorithm, is capable of achieving fault tolerance against multiple OC and SC faults. The proposed drive configuration is capable of delivering rated power to the BLDC motor even after the development of several faults in the power semiconductor switching devices. In this power converter, additional switching resources, provided to achieve fault tolerance, get connected only after the occurrence of faults. This feature avoids their unnecessary exposure before the occurrence of faults. Furthermore, the proposed topology requires fewer sensors to implement the fault diagnostic algorithm resulting in reduced cost and increased reliability. This article also presents an analysis that assesses the cost-effectiveness of the proposed drive configuration, which reveals that the additional cost to implement the proposed topology is not more than 6% of the total raw material cost of the conventional BLDC motor drive. Simulation and experimental studies validate the concept of the proposed drive configuration.

Investigating the input power quality of multi-pulse AC-DC power converter fed induction motor drives

Optimization of supply current total harmonic distortion (THD) of multi-pulse AC-DC power converter fed induction motor drive (IMD) is always a challenging issue. Higher amount of supply current THD degrades the input power quality of IMD. The supply current THD should be controlled in such a way so that it adheres the power quality standard of IEEE-519. With the increase of the pulse number of multi-pulse AC-DC converter, supply current THD increases. In this work, an investigation has been carried out on 6-pulse, 12-pulse, 18-pulse, and 24-pulse AC-DC power converters based IMD. A thorough analysis of input current profile, THD, dynamic responses including stator current, speed, torque profile of the induction motor are highlighted in this work with the various load perturbation conditions. This work will provide a message to the industrial community about the proper selection of AC-DC power converter for IMD application considering power quality and circuit configuration issues. All the investigating works are conducted in MATLAB/Simulink platform.

A Quasi-Z-Source-Based Space-Vector-Modulated Cascaded Four-Level Inverter for Photovoltaic Applications

This article proposes a single-stage buck–boost topology for photovoltaic (PV) applications with a three-phase output. This power converter is constituted by three quasi-Z-source (qZS) networks that are integrated with a four-level cascaded multilevel inverter (FCMI). Compared to the conventional multilevel inverter (MLI) configurations, such as the neutral-point-clamped (NPC) and the cascaded H-bridge (CHB) inverters, the proposed topology is structurally simple with lesser number of components. The proposed power converter and its modulation scheme enhance the boost factor by 50% compared to the aforementioned topologies while alleviating the voltage stress on the switching devices. It is shown that the proposed converter can regulate the output voltage in the stand-alone mode by controlling the shoot-through duty ratio of the qZS networks. Furthermore, it is shown that the proposed converter can be interfaced with the grid by controlling the modulation index along with the shoot-through duty ratio to achieve the twin objectives of maximum power point tracking (MPPT) and the unity power factor (UPF) operation with the grid. The simulation studies and experimentation on a scaled-down laboratory prototype verify the steady-state and dynamic performances of the proposed power circuit configuration and the associated control strategy.

An improved quasi Z‐source based H5 inverter with low leakage current for photovoltaic applications

Grid-connected Single-Stage Boost Inverters (SSBI) are extensively being researched in the area of photovoltaic energy conversion systems. Owing to their single-stage boosting capability, this class of power converters results in higher efficiency and reliability. This power circuit configuration is constituted by two mutually dependent sub-converters, in that a front-end quasi-Z-source (qZS) part is integrated to a back-end multilevel inverter (MLI). The MLI provides the shoot-through state to the qZS, while the qZS provides the pulsating DC input to the MLI. In general, solar photovoltaic inverters suffer from the disadvantage of leakage current that flows from solar panels to the grid/load. This paper introduces a dual quasi-Z-source based multilevel inverter, which achieves the following benefits: (a) five-level output voltage, (b) reactive power capability, (c) shoot-through immunity, (d) continuous input current, and (e) reduced leakage current based on VDE 0126-1-1 standards. In this paper, a modified modulation scheme, which is based on the employment of phase-disposed and level-shifted carrier signals, has been used to reduce the leakage current. To reduce the leakage current further, a passive filter is employed to eliminate high frequency variations across the parasitic capacitance. The working principle of the proposed power converter and the effectiveness of the modulation scheme have been validated with simulation studies in both standalone and the grid-connected mode. Finally, the simulation studies are verified through an experimental prototype of 500 W rating.

Basic Study of a Circuit Configuration for Power Transformer-less A. C. Fed Electric Trains using High Withstand Voltage Property of SiC Power Devices

The purpose of this study is to develop power circuits for AC electric trains with weight reduction and downsizing. We devised a new power circuit configuration which uses SiC modules for insulation function instead of the main transformers, manufactured the circuit models on an experimental basis, and executed the verification. The results verified the bidirectional operation, demonstrating that about a 5.7kW of power was transmitted for the input voltage of up to 200V and the switching frequency of 20kHz run, while ensuring the insulation state without any simultaneous conduction between the primary and secondary terminals through the flying capacitor.

A Four-Level Open-End Winding Induction Motor Drive With a Nested Rectifier–Inverter Combination With Two DC Power Supplies

This paper proposes a new nested rectifier–inverter circuit topology for a four-level (4-L) open-end winding induction motor drive (OEWIMD). To realize the 4-L inversion, the nested rectifier–inverter topology operates with unequal dc-link voltages, which are in the ratio of 2:1. The proposed topology has the inherent ability of avoiding the overcharging of the lower dc-link voltage capacitor by its higher voltage counter-part unlike in the case of the power circuit configuration proposed in the earlier literature. This paper also proposes a new sample-averaged zero-sequence elimination pulsewidth modulation (PWM) scheme for the proposed circuit configuration to avoid the flow of zero-sequence current through the motor windings. It is shown that the proposed power circuit is also capable of displaying immunity to a particular type of fault, as it can produce the same output voltage despite the unbalancing of one of the dc-link capacitor voltages without changing the modulation strategy. The proposed 4-L OEWIMD along with the associated PWM schemes is simulated and is validated with experimental results.

Improvised SVPWM Strategies for an Enhanced Performance for a Four-Level Open-End Winding Induction Motor Drive

A four-level open-end winding induction motor drive (OEWIMD) is obtained when an induction motor with open windings is fed from either side with two two-level 3-Ph voltage-source inverters (VSIs) with unequal dc-link voltages, which are in the ratio of 2:1. This drive principally suffers from two problems namely: the circulation of zero sequence current in motor phases and overcharging of the lower dc-link capacitor by its counterpart with higher dc-link voltage. It has been reported earlier, that the decoupled space vector pulse width modulation (SVPWM) control strategies avoid both of these problems. This paper proposes an improvised SVPWM scheme that achieves a better harmonic performance compared to the decoupled SVPWM scheme without altering either the power circuit configuration or the voltage ratings of the devices. The proposed PWM strategy clamps the inverter with lower dc-link voltage with an active state, while the other inverter is switched around it. It has been shown that the proposed SVPWM scheme results in an overall reduction of losses for the drive system while resulting in a considerably lower d <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> /d <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> compared to the decoupled SVPWM schemes. The four-level OEWIMD employing the proposed SVPWM scheme is simulated and is validated with experimental results.

Алгоритм термостабилизации силовых полупроводниковых приборов в электроприводе компрессора

A parametric approach for stabilizing the thermal state of power semiconductors in the converter for electrically driving the compressor used in subway trains is considered. Such an electric drive system is repeatedly switched in operation for a short period of time. The drive operates for approximately 5 min to fill the pneumatic system with compressed air, after which it is disconnected until the pressure in the system reduces due to compressed air consumption for braking the train or for opening and closing the doors. With such operation mode, semiconductors experience cyclic heating and cooling, due to which the problem of thermocycling is of significant importance for the power transistor modules used in such converter. Deviation of the crystal temperature above the transistor module substrate has a detrimental effect on the braze layer, causing it to become mechanically destructed and stratified, which eventually results in semiconductor failure. These features should be duly considered in selecting the power circuit configuration and in designing the converter. The compressor electric drive's power converter was designed at the Moscow Power Engineering Institute National Research University's Department of Automated Electric Drives. This converter comprises a step-down DC-to-DC converter producing a stable power supply voltage, a 3-phase inverter taking power supply from this voltage, and a du/dt filter. A thermal stabilization algorithm that has been implemented and tested at laboratory on a real power converter is proposed, the use of which makes it possible to reduce the temperature deviation of crystals in transistor modules. During the pause in the compressor duty cycle, the power converter is changed over to a special heating mode. The changeover to this mode is performed automatically without the need to use special control signals from the upper-level control system, nor does it need to make any additional switching operations in the electric drive's power circuits. The use of the proposed algorithm ensures uniform distribution of heat among all power semiconductors. The thermal images and temperature curves demonstrate the efficiency of this thermal stabilization algorithm in comparison with the usual control algorithm.

An SVPWM Scheme for the Suppression of Zero-Sequence Current in a Four-Level Open-End Winding Induction Motor Drive With NestedRectifier–Inverter

A four-level open-end winding induction motor (OEWIM) drive is known to suffer from two perennial problems. One is the problem of zero-sequence currentin the motor phases, which is caused by the existence of zero-sequence voltage in them. The other is the overcharging of the dc-link capacitor of theinverter operated with lower dc-link voltage by its counterpart operated with a higher dc-link voltage. This paper investigates the applicability of aspecial variant of space vector pulse width modulation (SVPWM) scheme for a recently proposed power circuit configuration, in which arectifier–inverter combination is nested within the conventional two-level inverter configuration to achieve four-level inversion. This PWM schemeis named as the sample-averaged zero-sequence elimination (SAZE) SVPWM scheme, wherein the zero sequence voltage is suppressed in each sampling timeperiod in the average sense. Both of the aforementioned problems encountered in this drive are successfully overcome for this power circuit configurationby resorting to the proposed SVPWM strategy.

Simple scheme to extract maximum power from series connected photovoltaic modules experiencing mismatched operating conditions

Solar photovoltaic (PV) arrays formed by series combination of several PV modules suffer from considerable reduction in power yield when subjected to mismatched operating conditions. To address this issue several schemes have been reported in the literature. Amongst these schemes, the distributed maximum power point tracking (DMPPT) schemes seem to be the most promising ones. However, majority of the existing DMPPT schemes employ voltage-equalisation technique, which cannot attain exact MPP for all the modules. To overcome this problem individual power measurement units are employed for each of the module but then it leads to the involvement of large number of sensors. Schemes which do not require modular level sensing have also been reported but they require to employ a very computational intensive control algorithm coupled with the need for precise communication. This study attempts to address these limitations by proposing a simpler DMPPT strategy. It requires only one conventional MPPT algorithm to extract maximum power from the overall system. The implementation of the scheme is carried out by utilising the power circuit configuration of the existing flyback-converter based standard DMPPT scheme. The viability of the scheme is ascertained through detailed simulation and experimental studies.

A Four-Level Inversion Scheme for a 6$n$-Pole Open-End Winding Induction Motor Drive for an Improved DC-Link Utilization

In this paper, a new power-circuit configuration for four-level inversion with an open-end winding induction motor is proposed. This configuration is suitable for an induction motor with 6 n (n = 1, 2,...) number of poles. Two isolated dc power supplies, each rated for one third of the total dc-link voltage, are sufficient to realize this four-level inverter scheme. It is shown that it is possible to produce a voltage vector of 1-p.u. magnitude with a total dc-link voltage of 0.66 p.u., indicating that the dc-link utilization is enhanced by a factor of 33% with this power-circuit configuration. In the proposed power circuit, the zero-sequence current is arrested as the motor phase windings of the open-end winding induction motor are segmented into two separate groups in the ratio of 2 : 1, with one end of each group forming an isolated neutral point. Each phase group is then powered by two individual two-level inverters with two separate dc-power supplies with a common negative rail. The existence of this common negative rail is the principal cause of an increased dc-bus utilization. A simple decoupled space-vector pulsewidth modulation is adequate to control both of these inverters, which further demonstrates the simplicity of the drive control.

Single-Phase DC-AC Boost Converter

This paper describes a new power conversion circuit topology for single-phase DC-AC boost converter, based on the dc-dc boost converter. It comprises an H-bridge, fed from a single input dc source through a boosting inductor. Change of load current flow is achieved with four current-steering diodes. The proposed boost inverter configuration performs single stage power conversion, which minimizes switching losses and attains higher efficiency as compared to the conventional boost inverter. The steady-state operating principle of the power circuit configuration and control strategy are described. A multi-loop structure controller is used to ensure a high dynamic performance. Computer simulations demonstrate the feasibility of the proposed boost inverter.http://dx.doi.org/10.4314/njt.v33i2.14

대기전력 저감형 LED 센서 조명시스템의 개발

In this paper, we propose a sensor-based LED lighting system that can significantly reduce standby powers. The proposed LED lighting system has the more advanced power circuit and control mechanism compared to existing one. The whole power circuit consists of two subcircuits. One is designed to apply electric powers to controller, PIR(Pyroelectric Infrared Ray) sensor and CdS, and the other one is designed to apply electric powers to LED module. Such a power circuit configuration makes the standby powers reduction of LED lighting system possible. From the experimental results, we confirmed that the standby powers saving performance of the developed power circuit is superior to that of the conventional one.

A Technical Survey on Control Strategies of Active Filter for Harmonic Suppression

In modern era, the tradition of non-linear loads in Electrical power system has sparked the research in power quality (PQ) concern like voltage flicker, voltage sag and swell, harmonics, etc., Among all the other concerns, one of the the majority significant of PQ problem is Harmonics .Active Power Filter (APF) is one of most challenging filter for the mitigation of harmonics. The heart of the Active power Filter is the controller part. In this study, a wide-ranging review of various controllers have been projected,Which mitigate harmonics, reactive power and unbalanced load currents originating from load side, and also the advantages and disadvantages of presented techniques are presented. The study also helps the researchers to select the optimum control strategies and power circuit configuration for APF applications.

Effect of Zero-Vector Placement in a Dual-Inverter Fed Open-End Winding Induction Motor Drive With Alternate Sub-Hexagonal Center PWM Switching Scheme

Three-level inversion can be achieved by the cascade connection of two two-level inverters to an open-end winding induction motor. Several space vector based pulsewidth modulation (PWM) control strategies have been proposed for this power circuit configuration in the past. It is known that space vector modulation offers a degree of freedom in its implementation with regard to the distribution of the zero-vector. In this paper, the effect of placement of zero-vector for the implementation of space vector based PWM techniques for a dual-inverter fed open-end winding induction motor drive is reported. Apart from constructing a consistent theoretical frame work, experimental results with continuous and discontinuous PWM are presented in this paper and all the cases are compared.

Comparative evaluation of two models of UPQC for suitable interface to enhance power quality

Majority of the dispersed generations from renewable energy sources are connected to the grid through power electronic interface, which introduce additional harmonics in the distribution systems. Research is being carried out to integrate active filtering with specific interface such that a common power quality (PQ) platform could be achieved. For generalized solution, a unified power quality conditioner (UPQC) could be the most comprehensive PQ protecting device for sensitive non-linear loads, which require quality input supply. Also, load current harmonic isolation needs to be ensured for maintaining the quality of the supply current. The present paper describes two control scheme models for UPQC, for enhancing PQ of sensitive non-linear loads. Based on two different kinds of voltage compensation strategy, two control schemes have been designed, which are termed as UPQC-Q and UPQC-P. A comparative loading analysis has developed useful insight in finding the typical application of the two different control schemes. The effectiveness of the two control schemes is verified through extensive simulation using the software SABER. As the power circuit configuration of UPQC remains same for both the model, with modification of control scheme only, the utility of UPQC can be optimized depending upon the application requirement.

Parallel converter scheme for high-power active power filters

A new topology for efficient utilisation of parallel converters as VAR compensators and active power filters (APF) for high power loads is proposed. Because of limited power handling capacity of individual devices, paralleling is the choice to increase rating of equipment, while keeping the THD of the current at the PCC within the agency specified standards. It has been reported in the literature that paralleling several converters, rather than switches, is more reliable in sharing of load. From this perspective, multilevel converters carry lot of weight, as their typical power circuit configuration limits the stress on individual devices to an appreciable extent. Also, they have the advantage of low switching frequency and full utilisation of switching devices, which is essential in high-power applications. These advantages have been utilised in parallel combination with a low-power high-frequency current-controlled APF, such that the higher order harmonics can be eliminated. A new parallel converter topology with a three-level neutral point clamped (NPC) converter and an auxiliary current-controlled VSI has been proposed and control techniques have been developed. Extensive simulation study have been carried out in a SABER simulator for linear and non-linear loads.