Power-aware Design Research Articles

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

This paper presents a high-density,129-channel, dual-‘hit’ FPGA-based time-to-digital converter (TDC) developed to implement the trigger-less data acquisition (DAQ) system for the Iron Calorimeter (ICAL) detector of the India-based Neutrino Observatory (INO) experiment. In this trigger-less DAQ scheme, the arrival time of signals from all the detector channels, about 3.6 million channels in the case of the INO-ICAL experiment, is required to be measured. This work, therefore, aimed at the development of a low-power, high-density TDC with uniform performance across the channels in the low-cost Spartan-6 FPGA. This TDC is based on tapped delay line (TDL) interpolation technique built using CARRY4 elements of the FPGA in the Spartan-6 FPGA-based DAQ system. In this TDC, a method for measuring the time-of-arrival of both the rising edge and subsequent falling edge (dual-hit) using a single channel is developed, thus allowing pulse width measurements. Here, a resource and power-aware design methodology is developed to arrive at the optimum values of the total number of delay elements in the TDL and clock frequency, facilitating the implementation of a large number of identical TDC channels. Further, in order to meet the area and timing constraints of the high-density TDC, semi-automatic placement scripts are developed with careful partitioning of the TDC channels. These aspects resulted in an implementation of the TDC with a least significant bit (LSB) resolution of 84.4 ps ± 2.5 ps, a dynamic range of 40 μs, time precisions (σ) across the channels in the range of 42 ps (0.49 LSB) to 58 ps (0.68 LSB), differential nonlinearity (DNL) of ±0.5 LSB and integral nonlinearity (INL) of [-0.49,0.84] LSB with a low power consumption of 7 mW per channel.

Power-aware VLSI design of reversible watermarking for access control

A lifting based reversible data hiding is introduced here. The low–high subband is subdivided into little blocks of size (4 × 4), to generate a content dependent watermark. Then the access management is done by permutation of the content dependent watermark by a user-specific covert key. The permuted watermark is employed to modulate the lifting coefficients of the low–high subband. The modulation causes degradation of the visual quality of the host image. That plays an important role in access management through inverse method. Lastly, a low-power ‘very-large-scale-integration’ architectural hardware of this scheme is designed and synthesized on a ‘field programmable gate array’. The experiment is conducted over a variety of benchmark images and the results establish the superiority of the method. It is also observed that in real-time processing, the scheme consumes 63.26% less power than the related implementation found in the literature, for watermarking encoder and decoder at a maximum operating frequency of 130.186 MHz for the processing of (512 × 512) sized images.

Logistic Function Based Memristor Model With Circuit Application

A new SPICE compatible memristor model is presented which is based on the solution to the well-known Logistic equation. Previously published first order function models are limited in their ability to elucidate the memristor's oscillatory and chaotic behavior. Fractional order models are not SPICE friendly although they are known to demonstrate chaos. The relationship between the logistic equation and its iterated map is used to show how the proposed model explains the memristor's oscillatory and chaotic characteristic. It emulates empirically observed ohmic and semiconducting response to temperature. The utility of the model is tested by implementing it in a novel reliability and power aware relaxation oscillator design. A methodical approach to estimating the oscillation frequency of such highly nonlinear circuitry is presented. Computed results are validated against the relaxation oscillator implemented in an LTSpice testbench.

Towards autonomous greenhouses solar-powered

Fuzzy logic controls have been used to develop intelligent control systems in greenhouses, leading to promote a comfortable microclimate for plant growth while saving energy and water resources. Solar energy is an effective solution to extend the use of these intelligent systems in isolated areas. In fact, this paper presents a practical solution based on the power-aware design for controlling the indoor environment of solar greenhouses. The system consists of feedback fuzzy logic controllers that log key field parameters using specific sensors and performs control actions for the environmental temperature, soil moisture, and relative humidity. With regard to the battery-coupled architecture of the solar system, the decision level is designed to consider the availability of operational resources before acting. Keeping in mind the constraint of low-cost, we propose a flexible design of an embedded system able to support remote management of the indoor environment key-parameters. The proposed control system was validated experimentally. The efficiency of the system was assessed by demonstrating significant energy and water savings as well as protection of solar system components from dry running issues

Model Based Energy Consumption Analysis of Wireless Cyber Physical Systems

Wireless mesh networks begin to be used as an infrastructure of cyber-physical systems. A critical issue in developing wireless cyber physical systems (WCPSs) is the limited amount of energy available in the nodes. Energy consumption analysis can help designer to conduct a power-aware design process. In this paper, we propose a model based energy consumption analysis framework at architecture level for WCPSs. We extract event chains from the architecture model. With the energy consumption model for processing each type of event, we can estimate the energy consumption for each control loop and each node, as well as the overall energy consumption. All these energy consumption indexes can help us to design a performance and energy consumption balanced WCPS.

FPGA emulation methodology for fast and accurate power estimation of embedded processors

Abstract Early estimation of application-specific power consumption has become one of the major constraints of modern ASIC design. While in early stages of the design process precise power consumption can only be obtained from very time consuming gate-level (GTL) simulation, power estimation methodologies aim to reduce computational overhead by deriving models to approximate power consumption on higher levels. This work presents an FPGA accelerated power estimation methodology for programmable processors based on a hybrid functional level (FLPA) and instruction level power analysis (ILPA) that can be mapped onto an FPGA together with the functional emulation. It enables fast and accurate estimation of application-specific power consumption and energy per task which is crucial for power-aware design of embedded processor architectures. The approach allows both hardware and software designers to optimize their implementations not only for processing performance but also for power efficiency. The power emulation methodology and considerations for the FPGA implementation of the power estimation is described in detail. Model validation against GTL power simulation and results are given for a typical embedded RISC processor and a commercial-grade Application Specific Instruction Set Processor (ASIP). Power consumption models yield fast and accurate power estimation with a %MAE of less than 9% and NRMSE of less than 7% enabling co-optimization of both hardware and software with respect to power consumption in early design stages.

Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems

Due to the growing complexity of Systems-on-Chip (SoC) and the increasing cost of their redesign and fabrication, industrials are urgently looking for design methodologies allowing them to identify issues early in the design flow and to explore the largest possible space of solutions. Several aspects should be taken into account in this context, among which power consumption is considered as a major concern. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach facilitates designers work by abstracting the energetic behavior of embedded systems through high-level models targeting an automatic generation of power-aware simulation code. It offers also the possibility to model dynamic power management aspects in order to use the corresponding generated code for DSE. This approach was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile and its simulator. This paper illustrates the proposed approach through a Software-Defined Radio (SDR) case study integrating the Dynamic Slack Reclamation (DSR) policy for dynamic power management. The processor power estimates obtained by the generated simulation code were compared to those obtained from physical implementation on the Xilinx Zynq-7000 platform. This comparison showed that our MDE approach allows to take efficient design decisions early in the design flow.

Multi-level energy/power-aware design methodology for MPSoC

Multiprocessor Systems-on-Chip (MPSoC) are becoming one of the most used solutions in order to meet the growing computation requirements of modern embedded applications. In such systems, power/energy consumption is a critical metric that should be taken into account in the design flow. System designers need an efficient power-aware design methodology and tools to cope with the complexity of MPSoC design. To address this challenge, we present in this paper a power-aware design methodology that relies on multi-level design space exploration. We propose a two-phase exploration process making profit first from functional-level simulations to reduce rapidly and significantly the solution space, and second from transactional-level simulations for better accuracy to select the most appropriate solution. Our methodology uses the same power modeling approach for the MPSoC at both the functional and transactional levels in order to guarantee the coherence of the estimation strategy. Furthermore, our methodology integrates runtime optimization techniques to reduce the energy/power consumption of the system. The efficiency of the proposed power-aware design methodology was demonstrated through a H.264 video decoder case study.

An Effective Combination of Power Scaling for H.264/AVC Compression

This brief proposes a novel method to determine the best combination of operation conditions for multiple power-scaling schemes. The power saving and rate-distortion performances of individual schemes are simulated, and then, the combined effects are modeled to obtain the best operation combination. The optimized combinations are defined as a power-level table. The proposed power-aware design is tested with four popular power-saving schemes and simulations show that a power saving of $\sim 25$ % is achieved at the sacrifice of <0.172dB Bjontegaard Delta peak signal-to-noise ratio degradation.

Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance &amp; power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

A Markov Decision Process Approach to Dynamic Power Management in a Cluster System

Dynamic power management (DPM) plays a significant role to save power consumption effectively in both the design and operational phases of computer-based systems. It is well known that the state-dependent control policy by monitoring energy states in each component or the whole system is efficient for power saving in server systems whose system state, such as transaction request, can be completely observed. In this paper, we consider an optimal power-aware design in a cluster system and formulate the DPM problem by means of the Markov decision process. We derive the dynamic programming equation for the optimal control policy, which maximizes the expected reward per unit electrical power, which is called the power effectiveness, and give the policy iteration algorithm to determine the optimal control policy sequentially. In numerical experiments, we show the optimal control policy for an example of a cluster system with two service nodes, where the arrival stream of the transaction request is described as a Markov modulated Poisson process. In addition, based on the access data of an enterprise system, the optimal power-aware control for the cluster system and its effectiveness is examined.

Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis

This paper involves the design and comparative analysis of Han-Carlson and Kogge-Stone adders in sub-threshold regime using three different hybrid logic families. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8, 16, 32 and 64 bit input data width. The proposed circuits show an energy efficient agreement with Spectre simulations using BSIM3v3 and BSIM4 models for 90nm CMOS technology at 0.4V supply voltage. The adder implementation outperforms its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional adders operated in the sub-threshold region.

Methodology for Power Implementation and Validation at Higher Level of Abstraction

In earlier generation of IC design technologies the prime parameters of concern were timing and silicon area. The increasing demand for high-performance, battery-operated, system-on-chips in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost, and reliability) to power consumption [1]. In recent years device densities and clock frequency have increased dramatically in devices thereby increasing the power consumption dramatically. During design process the most critical power requirements are tested only after power pins becomes explicit. There are different design strategies for reducing power consumption, and it also becomes critical to make power aware design even if power pins were not explicit or say at very abstraction level of design flow. UPF is used as an IEEE 1801 standard method which provides a consistent way to specifying power implementation intent throughout the design process [2]. Low power validation at very abstraction level uses RTL/Behavioral HDL model along with UPF intent. UPF provide an ability to verify the power intent behavior as early as possible or say at higher abstraction level by overlay the power behavior over the RTL/Behavior HDL model at same abstraction level. This paper describes how HDL model impacted at very higher abstraction level to meet certain power constraints and their validation using an industry accepted IEEE 1801 standard UPF low power validation flow. General Terms Power functionality, Abstraction level, Design flow, Power consumption, Logical functionality, Power implementation

A study on combinational effects of job and resource characteristics on energy consumption

By becoming more popular and complex, HPC systems like computational grids, clusters, clouds and the supporting data centers are now changed to remarkable energy consumers. A wide variety of researches, ranging from power-aware hardware design to developing optimized programs and to power-aware job scheduling, have been done hitherto in order to reduce their energy consumption. However, the success of these approaches highly depends to having a precise knowledge about power consumption behavior of the target system. In this paper, some neglected facts are shown about combinational effects of jobs' and resources' characteristics on energy consumption rate and define corresponding parameters which make these facts practically utilizable by formulating them as functions of job-machine characteristics. These facts are supported by the experimental analyses on real machines and analytical studies. The outcome of this paper can be exploited to have more energy efficient task mapping process in large-scale heterogeneous computational systems.

Tool chain for harvesting, simulation and management of energy in Sensorial Materials

The continuing decrease in size and energy demand of electronic sensor circuits allows endowing engineering structures and, to an increasing degree, materials with integrated sensing and data processing capabilities. Materials that adhere to this description are designated as Sensorial Materials. Their development is multidisciplinary and requires knowledge beyond materials science in fields like sensor science, computer science, energy harvesting, microsystems technology, low-power electronics, energy management, and communication. Development of such materials will benefit from systematic support for bridging research area boundaries. The present article introduces the backbone of an easy-to-use toolbox for layout of the energy supply of smart sensor nodes within a sensorial material. The fundamental approach is transferred from rapid control development, where a comparable MATLAB/Simulink tool chain is already in use. The main goal is to manage limited power resources without unacceptably compromising functionality in a given application scenario. The toolbox allows analysis of the modeled system in terms of energy and power and allows analyzing factors such as energy harvesting, use of predictive power estimation, power saving (e.g. sleep modes), model-based cognitive data reduction methods, and energy aware algorithm switching. It is linked to a simulation environment allowing analysis of energy demand and production in a specific application scenario. Its initial version presented here supports single self-powered sensor nodes. A broad set of application cases is used to develop scenario-dependent solutions with minimum energy needs and thus demonstrate the use of the toolbox and the associated development process. The initial test case is a large-scale sensor network with optical fiber–based data and energy transmission, for which optimization of energy consumption is attempted. The toolbox can be used to improve the power-aware design of sensor nodes on digital hardware level using advanced high-level synthesis approaches and provides input for sensor node and sensor network level.

Algorithms for the Multi-Period Power-Aware Logical Topology Design With Reconfiguration Costs

We tackle the problem of reducing power consumption in IP-over-WDM networks, targeting the power-aware logical topology design (LTD). Unlike the previous work in the literature, our solution reduces the power consumption with consideration of the cost (in terms of reconfigured traffic) incurred when the network is reconfigured. We first formulate the LTD with reconfiguration costs as an optimization problem. Then, we present three heuristics to effectively solve it. We compare our algorithms over an extensive set of networks and scenarios. Results indicate that our algorithms are effective in reducing power consumption while limiting the amount of traffic that is reconfigured. Moreover, we show that the input parameters are intuitive and easy to set, which makes our algorithms more practical.

Guest Editorial Special Section on Power-Aware Design for Embedded Systems

The papers in this special section present state-of-the-art power aware design for embedded systems. The articles examine recent developments used to address such topics as power consumption, power design, power requirements, energy management, and system performance.

Power-Aware Routing and Network Design with Bundled Links: Solutions and Analysis

The paper deeply analyzes a novel network-wide power management problem, called Power-Aware Routing and Network Design with Bundled Links (PARND-BL), which is able to take into account both the relationship between the power consumption and the traffic throughput of the nodes and to power off both the chassis and even the single Physical Interface Card (PIC) composing each link. The solutions of the PARND-BL model have been analyzed by taking into account different aspects associated with the actual applicability in real network scenarios: (i) the time for obtaining the solution, (ii) the deployed network topology and the resulting topology provided by the solution, (iii) the power behavior of the network elements, (iv) the traffic load, (v) the QoS requirement, and (vi) the number of paths to route each traffic demand. Among the most interesting and novel results, our analysis shows that the strategy of minimizing the number of powered-on network elements through the traffic consolidation does not always produce power savings, and the solution of this kind of problems, in some cases, can lead to spliting a single traffic demand into a high number of paths.

Energy-efficiency of protected IP-over-WDM networks with sleep-mode devices

Recently, the need for energy-efficient and sustainable capacity growth has become stringent for telecommunication networks and great efforts have been produced to reduce their power consumption. Optical technologies based on Wavelength Division Multiplexing are well-recognized as a promising solution for greening the future Internet. One relevant approach to achieve such power savings consists in aggregating traffic flows in few network links, so that power can be saved by switching-off some unused network devices. However, the need to ensure network resiliency against link and/or node failures imposes that still the resources reserved to protect connections become available immediately after a failure occurs. Therefore, a possible solution is to set some devices into low-power sleep-mode, so that they can be rapidly re-activated and provide fast connection recovery.In this paper we focus on the power-efficiency of protected IP-over-WDM networks and provide a comprehensive comparison of four different protection strategies, namely Shared-Link, Shared-Path, Dedicated-Link and Dedicated-Path Protection SLP, SPP, DLP and DPP respectively in a sleep-mode scenario. In the proposed design strategies we assume that low-power sleep-mode is enabled for devices used for protection. Mathematical models for a power-aware design with sleep-mode is proposed for the four protection strategies. We show that relevant power savings up to about 60% can be obtained for all the protection strategies by setting protection devices into sleep-mode.

Low Power Digital Alternative to Analog Control of Step-Down Converter

Power-aware design of digital controller for step-down converter is discussed and compared to a standard analog counterpart so as to verify the feasibility in System-on-Chip. A tri-mode digital controller IC in 0.35 μm CMOS process is presented to demonstrate such a solution including a PID, a so-called quarter PID and a robust RST compensator. The compensators respectively address the steady-state, stand-by and transient modes according to the operating conditions of the step-down converter. An idle-tone free condition for the Σ - Δ DPWM is considered to reduce the inherent tone noise under DC-excitation while generating a quasi-pure modulation signal compared to a traditional approach. Experimental results verify closed-loop performances and lead to a power assessment model suggesting feasible applications.