Power Amplifier Chip Research Articles

A V-Band Wideband Power Amplifier with High Gain in a 130 nm SiGe BiCMOS Process.

This paper introduces a high-gain wideband power amplifier (PA) designed for V-band applications, operating across 52 to 65 GHz. The proposed PA design employs a combination of techniques, including pole-gain distribution, base-capacitive peaking, and the parallel configuration of multiple small-sized transistors. These strategies enable significant bandwidth extension while maintaining high gain, substantial output power, and a compact footprint. A two-stage PA using the combination technique was developed and fabricated in a 130 nm SiGe BiCMOS process. The PA prototype achieved a peak gain of 27.3 dB at 64 GHz, with a 3 dB bandwidth exceeding 13 GHz and a fractional bandwidth greater than 22.2%. It delivered a maximum saturated output power of 19.7 dBm and an output 1 dB compression point of 18 dBm. Moreover, the PA chip occupied a total silicon area of 0.57 mm2, including all testing pads with a compact core size of 0.198 mm2.

Ultra-Wideband Transformer Feedback Monolithic Microwave Integrated Circuit Power Amplifier Design on 0.25 μm GaN Process.

This paper presents an ultra-wideband transformer feedback (TFB) monolithic microwave integrated circuit (MMIC) power amplifier (PA) developed using a 0.25 μm gallium nitride (GaN) process. To broaden the bandwidth, a drain-to-gate TFB technique is employed in this PA design, achieving a 117% relative -3 dB bandwidth, extending from 5.4 GHz to 20.3 GHz. At a 28 V supply, the designed PA circuit achieves an output power of 25.5 dBm and a 14 dB small-signal gain in the frequency range of 6 to 19 GHz. Within the 6 to 19 GHz frequency range, the small-signal gain exhibits a flatness of less than 0.78 dB. The PA chip occupies an area of 1.571 mm2. This work is the first to design a power amplifier with on-chip transformer feedback in a compound semiconductor MMIC process, and it enables the use of the widest bandwidth power amplifier on-chip transformer matching network.

A Gallium Nitride (GaN) Doherty power amplifier chip design based on series RC stability network

SummaryThis paper presents Doherty power amplifier (DPA) based on gallium nitride (GaN) technology, incorporating a parallel grounded network with series RC elements in front of the carrier and peaking amplifiers to enhance circuit stability. In comparison to the traditional series network with parallel RC structure, this configuration effectively reduces the sensitivity of the stability factor K to the capacitance value within the stability network. Consequently, it mitigates the impact on various performance indicators such as gain and drain efficiency, addressing the issue of measurement performance deviation caused by inaccurate capacitance models in the simulation files, which is particularly crucial for DPA. As a result, the circuit exhibits improved consistency in design and processing. With full band stability, the DPA achieves a saturation output power of approximately 29.8 dBm at 28 GHz, a saturation efficiency of 38.2%, and a 6‐dB back‐off efficiency of 29.6%.

A compact SiGe D-band power amplifier for scalable photonic-enabled phased antenna arrays

To address the rising demand for high-speed wireless data links, communication systems operating at frequencies beyond {100},hbox {GHz} are being targeted. A key enabling technology in the development of these wireless systems is the phased antenna array. Yet, the design and implementation of such steerable antenna arrays at frequencies over {100},hbox {GHz} comes with a multitude of challenges. In particular, the cointegration of active electronics at each antenna element poses a major hurdle due to the inherent space constraints in the array. This article proposes a novel scalable concept for opto-electronic phased antenna arrays operating at 140 GHz. It details the system architecture of a transmitter that enables the implementation of large scale, wideband, 2D steerable phased antenna arrays and presents the design and measurement of a compact SiGe power amplifier (PA) chip to be used as one of its key building blocks. The amplifier achieves a gain of 20 dB at 135 GHz, features a P_{1dB} of 14.6 dBm and can support data rates up to 45 Gbps in a limited footprint of only 540μm × 550μm. This makes it one of the fastest, most powerful D-band power amplifiers in literature with a footprint compatible with frac{lambda }{2}-spaced phased array integration.

Design of Power Amplifiers for BDS-3 Terminal Based on InGaP/GaAs HBT MMIC and LGA Technology.

With the development and popularization of the Beidou-3 navigation satellite system (BDS-3), to ensure its unique short message function, it is necessary to integrate a radio frequency (RF) transmitting circuit with high performance in the BDS-3 terminal. As the key device in an RF transmitting circuit, the RF power amplifier (PA) largely determines the comprehensive performance of the circuit with its transmission power, efficiency, linearity, and integration. Therefore, in this paper, an L-band highly integrated PA chip compatible with 3 W and 5 W output power is designed in InGaP/GaAs heterojunction bipolar transistor (HBT) technology combined with temperature-insensitive adaptive bias technology, class-F harmonic suppression technology, analog pre-distortion technology, temperature-insensitive adaptive power detection technology, and land grid array (LGA) packaging technology. Additionally, three auxiliary platforms are proposed, dedicated to the simulation and optimization of the same type of PA designs. The simulation results show that at the supply voltage of 5 V and 3.5 V, the linear gain of the PA chip reaches 39.4 dB and 38.7 dB, respectively; the output power at 1 dB compression point (P1dB) reaches 37.5 dBm and 35.1 dBm, respectively; the saturated output power (Psat) reaches 38.2 dBm and 36.2 dBm, respectively; the power added efficiency (PAE) reaches 51.7% and 48.2%, respectively; and the higher harmonic suppression ratios are less than -62 dBc and -65 dBc, respectively. The size of the PA chip is only 6 × 4 × 1 mm3. The results also show that the PA chip has high gain, high efficiency, and high linearity under both output power conditions, which has obvious advantages over similar PA chip designs and can meet the short message function of the BDS-3 terminal in various application scenarios.

Integrated biosensing system of electrochemistry and electrophysiology for cortisol and skin conductance analysis on smartphone

High level of mental stress will lead to negative psychological and health consequences, such as insomnia, depression, and cardiovascular disease, which will increase the suicide rate and affect social stability. Mental stress has been proved to be related to biomarkers cortisol and skin conductance, and reflects the complementary advantages of stress monitoring. Based on electrochemistry and electrophysiology analysis technology, combined with microelectronic design and biosensors, this paper constructed an integrated physiological and biochemical sensing system, and an intelligent user interaction system. Firstly, a molecularly imprinted biosensor with gold nanoparticles (AuNPs), prussian blue (PB), and polypyrrole (PPy), achieved highly sensitive detection of cortisol in the range of 1–10000 ng/mL and demonstrating good specificity. The cortisol detection unit used differential pulse voltammetry (DPV) method by dual power amplifier chip AD8674, which was a precision operational amplifier with low noise, low input bias current, and unit gain stability. Then, the skin conductance detection unit was mainly composed of a pulse width modulation (PWM) drive circuit, which was designed to achieve a 100 Hz voltage output. The integrated system was designed with microcontroller module, transimpedance amplifier (TIA) module, power management module, signal transmission module, cortisol and skin conductance detection module, which was suitable for constructing precision voltage control and weak current signal conditioning. Finally, based on the software and hardware platform of smartphones, an intelligent analysis system was developed to improve the portability and user interaction convenience. Our system achieved the physiological and biochemical joint detection for the first time, showing enormous application potential in future multimode sensing monitoring.

Hotspot thermal management of silicon-based high power hetero-integration

Extremely uneven thermal distribution due to the hotspots generating at the transistor channel regions on GaN power chip is one of the major obstacles to high power hetero-integration on silicon. In this work, a 12 mm × 18 mm × 0.7 mm embedded converging-diverging microchannel (CDMC) cooler silicon interposer (SI) is put forward to address the hotspot cooling. A 5.3 mm × 3.5 mm × 0.08 mm GaN monolithic microwave integrated circuit (MMIC) 3-stage power amplifier (PA) chip with DC heating power of ∼ 101 W was integrated on the SI to evaluate the on-chip hotspot cooling performance. The average hotspot heat flux was up to 306.8 ∼ 307.1 W/mm2, and the average chip heat flux achieved 545.4 ∼ 546.3 W/cm2. The maximum junction temperature of the GaN chip on CDMC SI was 137.2 ∼ 147.4 °C with the pressure drop of 122.8 ∼ 394.3 kPa and pumping power of 0.41 ∼ 3.29 W at 70 °C ambient temperature. The thermal and hydraulic characteristics of the CDMC SI are analyzed based on field synergy principle and thermodynamic properties using finite element method (FEM). The heat transfer coefficient (HTC) of the CDMC SI has 22.4 ∼ 35.4% increase compared with that of a typical microjet array (MJA) SI. The cooling performance and efficiency of the CDMC SI have been validated theoretically and practically to be prior to those of the MJA SI, and it is a promising solution for high power hetero-integration on silicon with brilliant hotspot thermal management capability.

Coplanar Asymmetry Transformer Distributed Modeling for X-Band Drive Power Amplifier Design on GaN Process

In this paper, a methodology for designing a distributed model for coplanar asymmetry transformer on gallium nitride (GaN) process is proposed, which can accurately characterize the transformer’s feature up to a millimeter-wave band. The paper analyses a transformer-based matching circuit and proposes a practical transformer design procedure. A two stage, transformer matching based X-band power amplifier (PA) is reported here. Using the proposed transformer model and correlated transformer design procedure can sharply reduce schematic design period and optimum process time. The PA chip is designed on a 0.25 µm GaN technology process and occupies a 1.515 mm2 area. At a 28 V supply, the gain and output power of the PA reaches 15 dB and 29 dBm respectively, and the wideband matching transformer reaches 47.6% bandwidth. To the best of our knowledge, the distributed model for coplanar asymmetry transformer and transformer-based X-band MMIC PA on GaN process in this work is the first case among the reported papers.

A Compact 60GHz Power Amplifier in 65nm CMOS Technology

A compact 60GHz power amplifier chip in 65nm CMOS technology of three-stage common source structure is presented. The first two amplifiers offer sufficient gain to pre-amplify the small input power. The third stage amplifier uses two sets of differential pairs to achieve power synthesis. On-chip transformer coupling is adopted to realize inter-stage impedance matching as well as input and output matching. The compact structure of on-chip transformer can reduce the chip size and improve the integration degree. The measured small signal gain at 60GHz of 22.3dB, the saturation power of 20.2dBm, the output P-1dB of 17.3dBm, the PAE of 14%, and the core area is 0.19mm2. The power amplifier can be used in high-speed short-range wireless communication system to enhance communication data transmission capacity.

Quantum near field probe for integrated circuits electromagnetic interference at wafer level

With the complexity and integration of integrated chips increasing, existing integrated circuits electromagnetic interference techniques using metallic probes cannot meet the emerging demand at single die level or wafer level, which requires micron spatial resolution and ultraweak invasiveness. In this article, we developed a non-invasive near field probe in the fiber format using nitrogen-vacancy center in diamond, which was attached to the tip of fiber as microwave B-field sensing element. Subsequently, we applied the fiber diamond probe to near field scanning of a low noise amplifier chip and a power amplifier chip. Through numerical simulation, we find that the surface field strength is proportional to current density at chip surface, thus this probe can be used as a current imaging technique at microwave frequency.

Design of millimeter wave radar amplification module

In this paper, the millimeter wave radar amplification device is designed using the MWG303 power amplifier chip of Milliway Electronic Technology Co., Ltd. The whole device comprises an input waveguide microstrip transition structure based on Rogers 5880 and an output waveguide microstrip transition structure based on quartz. And waveguide structures such as waveguide turn and waveguide lift, in this design, the waveguide microstrip transition circuit is designed and simulated in the 3D electromagnetic field simulation software HFSS of Ansoft Company, and then the parts are combined, and the micro-assembly test is carried out after CAD processing. The results show that the gain can reaches more than 10dB. The design has the advantages of high gain, good flatness, practical structure and so on.

Analysis of Process Variations in W-Band GaN MMIC PAs Using Nonparametric Statistics

This article presents an analysis of the effects of amplifier process-related performance variation on the radiation patterns of a W-band active transmit antenna array. Based on measured on-wafer S-parameters for about 80 amplifier chips designed in an experimental 90-nm gallium nitride (GaN) on SiC process, a statistical analysis of the array patterns is performed. Several types of probability density functions (pdfs) are generated from measured data and compared to determine which statistical approach is most relevant. We find that a joint distribution that maintains the correlation structure between |S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> | and ∠S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> is important for an accurate analysis. The monolithic microwave integrated circuits (MMICs) are connected to the waveguide-fed horn antenna elements in the array via microstrip-to-waveguide transitions fabricated on alumina. The transitions are analyzed in full-wave simulations with fabrication tolerances included in the analysis. Finally, the MMIC and transition statistical variations are cascaded, resulting in a quantitative evaluation of spatial power combining. Given a random choice of power amplifier chips in a 4×4 array, the EIRP is shown to vary by ±3 dB at 94 GHz.

Fully integrated CMOS tunable power amplifier using reconfigurable input/interstage/output matching networks

This paper presents a two-stage tunable power amplifier (PA) fully-integrated in 130 nm CMOS process. This multi-band PA consists of reconfigurable input, interstage, and output matching networks in order to tune the center frequency in use. The proposed tunable power amplifier enables three different bands with center frequency of 900 MHz, 1450 MHz, and 1900 MHz. By switching these bands, the designed power amplifier covers frequency range of 700 MHz–2200 MHz known as Long-Term Evolution mobile network. As a result, the proposed tunable power amplifier obtains small-signal gain (S21) of 27.8 dB/29.4 dB/28.6 dB, saturated output power (Psat) of 22.4 dBm/23.0 dBm/23.2 dBm, and power added efficiency of 21.0%/23.7%/25.0% at three targeted frequency bands, respectively. The proposed fully-integrated triple-band power amplifier chip layout occupies an area of 2.25 mm2 including bond pads.

A 2–20-GHz 10-W High-Efficiency GaN Power Amplifier Using Reactive Matching Technique

In this article, we present the analysis, design, and implementation of a wideband 10-W monolithic microwave integrated circuit power amplifier (PA), fabricated in a low-cost 0.1-μm gallium nitride (GaN) on Si technology. The design is focused on the realization of a low-loss and wideband impedance transformation networks across 2-20 GHz using a reactive matching (RM) technique. The two-stage GaN PA achieves an average output power of 40.1 dBm and a peak output power of 41.6 dBm at 13 GHz, in the CW-mode operation, with a smallsignal gain of S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> > 25.5 dB over the entire bandwidth. The average power-added efficiency (PAE) is 21%, with a peak PAE of 29% at 6 GHz. The PA chip occupies an area of 2.9×2.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the best of our knowledge, the PA presented in this work demonstrates the highest broadband gain among the reported GaN-based RMPAs with a corresponding output power of about 10 W.

Active Integrated Dielectric Resonator Antenna-in-Package Design

This letter proposes a packaged active integrated dielectric resonator antenna-in-package (AIDRAiP), which consists of a hollow rectangular dielectric resonator antenna (RDRA), and internally packaged power amplifier and bandpass filter chips. First, a modified annular slot feeding structure is proposed to design an RDRA with a wide −10 dB bandwidth of 20.6%. Then, by integrating an amplifier and a filter chip into a hollow RDRA, a well-packaged AIDRAiP is developed with the circuits and antenna on the same side of a substrate. The size of the AIDRAiP is the same as that of the hollow RDRA. A −10 dB band of 2.38–2.52 GHz (determined by the bandpass filter) and a gain of about 15.0 dBi are achieved for the AIDRAiP prototype, with a reasonable agreement obtained between the measured and cosimulated results.

A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’s output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation. And the coupling coefficient ( $k$ ) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power ( $P_{\mathrm {sat}}$ ), and 12.9-dBm output 1-dB compression point ( $P_{\mathrm {1\,dB}}$ ). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz).

CMOS Power Amplifier on Top of Embedded Transformer for Compact Module

A small-sized high-performance complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) module is presented. To reduce insertion loss of the output matching network (OMN), an off-chip transformer is designed on a FR-4 printed circuit board (PCB). To minimize the area of the OMN, the transformer is embedded underneath the PA chip. Coupling between the PA and the transformer is minimized so that the performance is not affected. For the 7.5 dB peak-to-average power ratio, 16-QAM long-term evolution signal, the proposed CMOS PA module achieves a power-added efficiency of 38.5% and an adjacent channel leakage ratio level under ${-}31$ dBc at an average output power of 27.5 dBm. The proposed technique can be used in any wireless Tx applications requiring small form-factor and high performance.

Research of Drives of Power Amplifiers of Magnetic Levitation Servo Spindle Applied to Micro EDM Based on FPGA

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

A broadband power-combined amplifier based on multi-stage probe-pair traveling-wave power divider/combiner at Ka-band

A multi-stage traveling-wave waveguide-based spatial power divider/combiner using waveguide-to-microstrip (Wg-Ms) probe-pair coupling structure is proposed and applied to the design of a broadband power-combined amplifier module at Ka-band. An eight-way passive back-to-back power divider-combiner with four-stage Wg-Ms probe-pair transitions has been designed, fabricated, and tested. The measured overall insertion loss is less than 1.5 dB from 28 to 40 GHz, which demonstrates the low-loss performance of the proposed multi-way dividing/combining structure. Based on the passive power divider/combiner, an eight-device power-combined amplifier has been implemented with eight broadband medium power amplifier chips. The measured small-signal gain of the amplifier is more than 18 dB and the output power at 1-dB gain compression (P-1 dB) is higher than 30 dBm in the frequency band of 28–40 GHz. Power combining efficiency is within the range of 76–88%. Furthermore, the performance degradation of the power-combined amplifier due to device failure is also analyzed and tested. The experimental result indicates the reliability of this type of power-combined amplifier.

Design of a Sawtooth Generator Applied for Class-D Audio Power Amplifier

A systematic introduction to principles and advantages of the class-D audio amplifier based on pulse width modulation (PWM) are presented in this paper. The traditional sawtooth generator needs voltage-regulator tube to server as a core component. Against to such a disadvantage a simple way based on the charging and discharging capacitance is proposed to achieve sawtooth generator. The circuit design is based on SIMC 0.18um process. Spectre simulation results show that the sawtooth generator's performance is good. And it suits for the design of class-D audio power amplifier chip.