Post-processing Unit Research Articles

Josephson junction oscillator embedded in the microcontroller: Pseudo-random number generation and combination synchronization

Dynamical scrutiny of the resistive capacitive inductive shunted Josephson junction (JJ) oscillator (RCLSJJO), microcontroller realization, pseudo-random number generation (PRNG) and combination synchronization are achieved in this paper. Numerical probing led to the establishment that the RCLSJJO is characterized by regular behaviors, bistable periodic-2-oscillations, periodic bursting characteristics and various shapes of chaotic dynamics. Thereafter, the vast dynamical characteristics obtained theoretically are realized by the microcontroller realization with qualitative agreements. Moreover, a chaos-based PRNG is designed by using chaotic RCLSJJO and linear feedback shift register (LFSR) as post-processing unit. Satisfactory results are obtained from the NIST 800–22 test suite and the randomness of binary data generated from the proposed RCLSJJO-based PRNG is confirmed for chaos-based digital applications. Lastly, the combination chaos synchronization of two drive and one response RCLSJJO is proven thanks to the theoretical analysis.

Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling

The new generation of electronic circuits based on spintronic technology have drawn the attention of researchers in recent years due to their remarkable features, including low-power consumption, non-volatility, and compatibility with the CMOS technology. However, these circuits usually rely on the pre-charge sense amplifier (PCSA), to read the state of the magnetic tunnel junctions (MTJ). The major disadvantage of the PCSAs is the high sensitivity of these circuits to inputs scheduling. It means that if the inputs are not applied to the circuit exactly in the specified time, the generated output will not be valid. This issue causes a serious problem in the ripple carry adders due to their carry propagation. In this paper, a novel structure is proposed which is based on removing MTJ from carry propagation path by adding a post-processing unit. The proposed post-processing unit makes the spintronic adders invulnerable to inputs scheduling. The proposed adder in this paper occupies at least 29% less area. It also offers 40% lower carry propagation delay, and 37% lower power-delay product compared to the efficient state of the art counterpart.

An Instruction-Driven Batch-Based High-Performance Resource-Efficient LSTM Accelerator on FPGA

In recent years, long short-term memory (LSTM) has been used in many speech recognition tasks, due to its excellent performance. Due to a large amount of calculation and complex data dependencies of LSTM, it is often not so efficient to deploy on the field-programmable gate array (FPGA) platform. This paper proposes an LSTM accelerator, driven by a specific instruction set. The accelerator consists of a matrix multiplication unit and a post-processing unit. The matrix multiplication unit uses staggered timing of read data to reduce register usage. The post-processing unit can complete various calculations with only a small amount of digital signal processing (DSP) slices, through resource sharing, and at the same time, the memory footprint is reduced, through the well-designed data flow design. The accelerator is batch-based and capable of computing data from multiple users simultaneously. Since the calculation process of LSTM is divided into a sequence of instructions, it is feasible to execute multi-layer LSTM networks as well as large-scale LSTM networks. Experimental results show that our accelerator can achieve a performance of 2036 GOPS at 16-bit data precision, while having higher hardware utilization compared to previous work.

AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS

As a widely used speech-triggered interface, deep-learning-based keyword spotting (KWS) chips require both ultra-low power and high detection accuracy. We propose a sub-microwatt KWS chip with an acoustic activity detection (AAD) to achieve the above two requirements, including the following techniques: first, an optimized feature extractor circuit using nonoverlapping-framed serial Mel frequency cepstral coefficient (MFCC) to save half of the computations and data storage; second, a zero-cost AAD by using MFCC’s 1st-order output to clock gate neural network (NN) and postprocessing (PP) unit, with 0 miss rate; third, a tunable detection window to adapt to different keyword lengths for better accuracy; and finally, a true form computation method to decrease data transitions and optimized PP. Implemented in a 28-nm CMOS process, this AAD-KWS chip has a 0.4-V supply, an 8-kHz frequency for MFCC, and a 200-kHz frequency for other parts. It consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.36~\mu \text{W}$ </tex-math></inline-formula> in quiet scenarios when AAD is enabled and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.8~\mu \text{W}$ </tex-math></inline-formula> in normal scenarios, where the MFCC circuit consumes only 170 nW. Its accuracy reaches 97.8% for two keywords in the Google Speech Command Dataset (GSCD).

FPGA modeling of a novel fully-synthesizable and secure TRNG based on key-dependent s-box

In this study, the Field Programmable Gate Array (FPGA) implementation of a True Random Number Generator (TRNG) using dynamic key-based s-box architecture as a post-processing technique is presented. In the proposed architecture, the post-processing method of TRNG consists of two different functions, in a total of 32x32 (32-bit input & 32-bit output), containing four independent 8x8 (8-bit input & 8-bit output) s-boxes. Raw random numbers are subjected to three-stage substitution operations in these functions, and their statistical properties are cryptographically improved. The post-processing unit of TRNG is compressionless as the s-boxes are 8 x 8. Thanks to this distinctive feature of the proposed method, TRNG can reach a final output bit rate of 250 Mbps with an entropy of 0.99. With the same output bit rate, TRNG passes the National Institute of Standard and Technology (NIST) Special Publication (SP) 800-22 statistical randomness evaluation tests with success above the minimum confidence interval of 0.9805. In addition to the NIST tests, bias, entropy, correlation, chi-square, and true randomness analyses are also given for TRNG's cryptographic verification. Besides to the statistical requirements, cost and performance analyses for TRNG are also presented in the study. The estimated dynamic power consumption for TRNG needing a low chip area of 2% (3221 LEs) for hardware implementation, is measured as 10.2 mW. The final results show that TRNG has high security and efficiency standards and can be used successfully in embedded cryptographic applications.

Design and Implementation of a flexible Multi-purpose Cryptographic System on low cost FPGA

The design of cryptographic hardware that supports multiple cryptographic primitives is common in literature. In this work, a new design is presented consisting of a multi-purpose cryptographic system featuring both 128-bit pipelined AES-CORE (Advanced Encryption Standard) for high-speed symmetric encryption and a Keccak hash core on a low-cost FPGA. The KECCAK-CORE’s security and performance parameters are tunable in the sense that capacity, bitrate, and the number of rounds can be user-defined. Such flexibility enables the core to suit a large range of security requirements. The structure of Keccak’s sponge construction is exploited to enable different modes of operation. An example application outlined in this work is Pseudo Random Number Generation (PRNG). With few adjustments, the KECCAK-CORE was also operated as a post-processing unit for True Random Number Generation (TRNG) that uses the analog Lorenz chaotic circuit as a physical entropy source. The multi-purpose design was implemented in VHDL targeting an IntelFPGA Cyclone-V FPGA. For AES symmetric encryption, a maximum throughput of 31.1Gbps was achieved and a logic usage of 25146LEs (23% of the FPGA) in the case of the pipelined variant of AES-CORE. For the KECCAK-CORE, maximum throughput figures of 5.81, 8.4, and 11Gbps were achieved for the three SHA-3 variants 512, 384, and 256-bit respectively, with an area usage of 8947LEs (8%). The system as a whole occupies an area of 26909LEs (26%). The random sequences generated by the system operating in PRNG and TRNG post- processing modes successfully passed the National Institute of Standards and Technology (NIST) statistical test suite (NIST SP 800-22). The information entropy analysis performed on the post-processed TRNG sequences indicates an average of 0.935.

Intelligent Path-Selection-Aided Decoding of Polar Codes

CRC-aided successive cancellation list (CA-SCL) decoding is a powerful algorithm that dramatically improves the error performance of polar codes. Path selection is a major issue that affects the decoding latency of SCL decoders. Generally, path selection is implemented using a metric sorter, which causes its latency to increase as the list grows. In this paper, intelligent path selection (IPS) is proposed as an alternative to the traditional metric sorter. First, we found that in the path selection, only the most reliable paths need to be selected, and it is not necessary to completely sort all paths. Second, based on a neural network model, an intelligent path selection scheme is proposed, including a fully connected network construction, a threshold and a post-processing unit. Simulation results show that the proposed path-selection method can achieve comparable performance gain to the existing methods under SCL/CA-SCL decoding. Compared with the conventional methods, IPS has lower latency for medium and large list sizes. For the proposed hardware structure, IPS's time complexity is O(klog2(L)) where k is the number of hidden layers of the network and L is the list size.

A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction

This work presents the world’s first neural signal processor for seizure prediction, which includes a preprocessing unit, a feature extractor, a reconfigurable support vector machine (SVM) kernel, and a postprocessing unit. Seizure prediction performance is enhanced by on-chip training for model adaptation. Design optimization is applied across the layers of abstraction to minimize the area and energy. The area of the feature extractor is reduced by 28% with an approximated energy operator (AEO). The proposed scaling-based Newton–Raphson (NR) divider reduces the required number of iterations for division by 62.5%. For alternating direction method of multipliers (ADMM)-based SVM training, the computational complexity is reduced by up to 99.9% through pointer-based matrix multiplication. By leveraging the LDL decomposition, 80% multiplications for updating weights are saved. The chip achieves a seizure prediction performance with a 92.0% sensitivity and a 0.57/h false alarm rate (FAR). The training latency is 8.44 ms with a power dissipation of 2.31 mW at 6.05 MHz. Compared with an ARM Cortex-M3 microcontroller, this work achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$124\times $ </tex-math></inline-formula> higher area efficiency and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$299\times $ </tex-math></inline-formula> higher energy efficiency. The chip also supports seizure detection and achieves a sensitivity of 98.6% and an FAR of 0.18/h, exceeding the state-of-the-art designs.

Performance investigation and collaborative optimization of power, economy and NOx removal for waste heat cascade utilization system in ocean-going vessels

Waste heat recovery technology of ships is meaningful for the enhancement of system efficiency and protection of environment. Compared with conventional diesel engines, the natural gas engines have the advantage of low emission, and its exhaust gas with quite high temperature is very suitable for utilization as the heat source of cascade waste heat system. This study integrates an over-expansion transcritical CO2 cycle with a double effect absorption refrigeration cycle to recover the heat energy from a natural gas engine. At the same time, a post-processing unit is proposed to remove the nitrogen oxide of flue gas. The research results indicate that the higher engine load contributes to improving the equivalent output work and economy of the combined cycle while the post-processing unit can further reduce the payback time under the given conditions. In terms of the parameters analyses, the turbine outlet pressure of transcritical cycle has an optimal value of 2.25 MPa, which can make the output work to reach the maximum value of 305.0 kW, and the performance improvement of refrigeration cycle can be achieved by decreasing the temperature of high pressure generator or increasing the temperature of low pressure generator. After multi-objective optimization, the residual equivalent output work, payback period and amount of NOx reduction of the total system are 150.77 kW, 4.20 years and 8.16 g/kWh, respectively. In addition, the Energy Efficiency Existing Ship Index is further reduced to 8.21 gCO2/ton·nm with the aid of the proposed system.

Theoretical Circuit Design of an Efficient Spintronic Random Number Generator With an Internal Postprocessing Unit

In this paper, a spintronic true random number generator (<b>TRNG</b>) is designed using the stochastic switching feature of the Magnetic Tunnel Junction (<b>MTJ</b>) device in the sub-critical current regime. The proposed structure consumes low power and occupies a small area. Also, to improve the quality of random numbers production and compensate for the impact of process variations on the quality of the random output, the proposed TRNG includes an internal post-processing unit. Compared to state-of-the-art designs, using an internal post-processing unit reduces the proposed generator&#x0027;s area overhead and power consumption. The simulation results show that the TRNG proposed in this paper consumes up to 68&#x0025; less power and occupies up to 64&#x0025; smaller area than the state-of-the-art design. Also, due to the existence of the efficient post-processing unit, the proposed TRNG successfully passes the national institute of standards and technology (NIST) random number tests even in the presence of the fabrication process variations.

FPGA implementation and image encryption application of a new PRNG based on a memristive Hopfield neural network with a special activation gradient

A memristive Hopfield neural network (MHNN) with a special activation gradient is proposed by adding a suitable memristor to the Hopfield neural network (HNN) with a special activation gradient. The MHNN is simulated and dynamically analyzed, and implemented on FPGA. Then, a new pseudo-random number generator (PRNG) based on MHNN is proposed. The post-processing unit of the PRNG is composed of nonlinear post-processor and XOR calculator, which effectively ensures the randomness of PRNG. The experiments in this paper comply with the IEEE 754-1985 high precision 32-bit floating point standard and are done on the Vivado design tool using a Xilinx XC7Z020CLG400-2 FPGA chip and the Verilog-HDL hardware programming language. The random sequence generated by the PRNG proposed in this paper has passed the NIST SP800-22 test suite and security analysis, proving its randomness and high performance. Finally, an image encryption system based on PRNG is proposed and implemented on FPGA, which proves the value of the image encryption system in the field of data encryption connected to the Internet of Things (IoT).

A Proposal of Implementation of Sitting Posture Monitoring System for Wheelchair Utilizing Machine Learning Methods.

This paper presents a posture recognition system aimed at detecting sitting postures of a wheelchair user. The main goals of the proposed system are to identify and inform irregular and improper posture to prevent sitting-related health issues such as pressure ulcers, with the potential that it could also be used for individuals without mobility issues. In the proposed monitoring system, an array of 16 screen printed pressure sensor units was employed to obtain pressure data, which are sampled and processed in real-time using read-out electronics. The posture recognition was performed for four sitting positions: right-, left-, forward- and backward leaning based on k-nearest neighbors (k-NN), support vector machines (SVM), random forest (RF), decision tree (DT) and LightGBM machine learning algorithms. As a result, a posture classification accuracy of up to 99.03 percent can be achieved. Experimental studies illustrate that the system can provide real-time pressure distribution value in the form of a pressure map on a standard PC and also on a raspberry pi system equipped with a touchscreen monitor. The stored pressure distribution data can later be shared with healthcare professionals so that abnormalities in sitting patterns can be identified by employing a post-processing unit. The proposed system could be used for risk assessments related to pressure ulcers. It may be served as a benchmark by recording and identifying individuals’ sitting patterns and the possibility of being realized as a lightweight portable health monitoring device.

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

This study presents a novel Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized designs have been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. Two separate TRNG designs have been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequency of the TRNG with 32-bit IQ-Math fixed point number standard is 344.585 MHz and the throughput is approximately 344 Mbit/s. The maximum operating frequency of the TRNG with 32-bit IEEE 754-1985 floating point number standard is 316.756 MHz and the throughput is 316 Mbit/s. 1 Mbit sequence has been generated by both designed TRNG systems. Randomness analysis of the generated numbers has been performed in accordance with the NIST 800-22 tests and the generated numbers have successfully passed all of the tests.

Harvard architecture based post processed True random number generator

The True random number generation (TRNG) is a process which takes different physical quantities that should be non-deterministic in nature and then they are post processed to reduce potential biases in the random number generation process. The true random number generators are used in various applications like security, cryptography, computer simulation and gaming applications. This work proposed a unique and powerful approach to get random numbers on FPGA by using an unsystematic jitter of ring oscillators. In order to get wide range of variations in the oscillations and to inject jitter into the generated ring oscillator clocks, the free running oscillator rings integrate programmable delay lines (PDL). The primary advantage of the proposed true random number generator is that it regulates the resemblance between many ring oscillators and so it improves the randomness qualities by using PDL. Furthermore, a Harvard architecture based post processing unit is used to eradicate similarities in the generated random numbers. Validation of the suggested solution synthesized on Xilinx with the support of Verilog HDL, and the parameters in terms of area, delay and power are also analyzed.

Dynamic Modeling and Control of a Coupled Reforming/Combustor System for the Production of H2 via Hydrocarbon-Based Fuels

The present work aims to provide insights into the dynamic operation of a coupled reformer/combustion unit that can utilize a variety of saturated hydrocarbons (HCs) with 1–4 C atoms towards H2 production (along with CO2). Within this concept, a preselected HC-based feedstock enters a steam reforming reactor for the production of H2 via a series of catalytic reactions, whereas a sequential postprocessing unit (water gas shift reactor) is then utilized to increase H2 purity and minimize CO. The core unit of the overall system is the combustor that is coupled with the reformer reactor and continuously provides heat (a) for sustaining the prevailing endothermic reforming reactions and (b) for the process feed streams. The dynamic model as it is initially developed, consists of ordinary differential equations that capture the main physicochemical phenomena taking place at each subsystem (energy and mass balances) and is compared against available thermodynamic data (temperature and concentration). Further on, a distributed control scheme based on PID (Proportional–Integral–Derivative) controllers (each one tuned via Ziegler–Nichols/Z-N methodology) is applied and a set of case studies is formulated. The aim of the control scheme is to maintain the selected process-controlled variables within their predefined set-points, despite the emergence of sudden disturbances. It was revealed that the accurately tuned controllers lead to (a) a quick start-up operation, (b) minimum overshoot (especially regarding the sensitive reactor temperature), (c) zero offset from the desired operating set-points, and (d) quick settling during disturbance emergence.

Overall performance analysis and GRA optimization of solar air heater with truncated half conical vortex generators

The present numerical study using ANSYS FLUENT 18.1 is based on improving the thermohydraulic performance of a solar air heater by embedding truncated half conical vortex generators (THC-VGs) on the absorber plate. Grey relational analysis (GRA) optimization technique is employed to achieve the best configuration for the applicable range of Reynolds number (Re = 3500–16000). The THC-VGs are fixed on the absorber plate at a relative pitch ratio, P/e range of 2.67–6.67 and placed such that the angle of attack, α lies in between 0° and 90°. RNG k-ε turbulent model is employed to solve the complex governing equations of CFD. Results are analysed by computing different performance parameters like, Nusselt number, Nu, thermal enhancement factor, TEF, friction factor, f, friction factor enhancement factor, FEF and thermohydraulic performance parameter, THPP. A maximum percentage enhancement of 187% in Nu is noted for α = 60°, P/e = 2.67 and Re = 16000. Results are supported with proper justifications by using different contours derived from the post processing unit of the CFD code. Proper flow dynamics along with thermal behaviour due to the introduction of THC-VGs are explored. Correlations for Nu and f are developed as a function of Re, P/e and α.

Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator

In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated by uniting the chaotic system-based RNG and the RO-based RNG structures on FPGA. The chaotic oscillator structure as the basic entropy source has been implemented in VHDL using Euler numerical algorithm in 32-bit IQ-Math fixed point number standart on FPGA. The designed chaotic oscillator has been synthesized for the FPGA chip and the statistics related to chip resource consumption and clock frequencies of the units have been presented. The RO-based RNG structure has been designed as the second entropy source. Chaos-ring based dual entropy core novel TRNG unit have been created by combining of these two FPGA-based structures in the XOR function used at the post processing unit. The throughput of the designed dual entropy core TRNG unit ranges 464 Mbps. The output bit streams obtained from FPGA-based novel TRNG have been subjected to NIST 800-22 test suites.

Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks

This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity-based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity-based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity-based TRNG circuit has been demonstrated. XOR gate-based post-processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm 2 and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity-based circuit design makes the proposed TRNG robust against reverse engineering attacks.

Operational strategy of high rate anaerobic digester with mixed organic wastes: effect of co-digestion on biogas yield at full scale

ABSTRACTThe present research work is aimed at providing an economically feasible solution for the farmers to exploit the mixed organic wastes (MOW) as resources for the generation of biogas based electrical power and utilize the same for irrigation purpose to reduce the dependence on electricity board. A full scale biomethanation plant has been installed based on anaerobic gas lift reactor (AGR) technology to analyse, understand the operational parameters of anaerobic digestion and assess the performance of a high rate biomethanation plant by co-digesting the MOW such as poultry litter (PL), cattle manure (CM) and napier grass (NG) at ambient temperature. The biomethanation plant was incorporated with inline pre and post-processing unit assembly. The plant was fed with 1000 kg of MOW per day having 250 kg of total solids, about 178–200 kg of volatile solids and operated continuously for 52 weeks under ambient temperature. Electrical power generated (84.5–104 kWh/day) from biogas (65–80 m3/day) containing methane (40–48 m3/day) was used for operating the water pumps for agricultural purpose and the digestate (115–130 kg/day) was exploited as organic manure for growing crops in the same field. Napier grass was grown in the same land and other feedstocks were procured from the nearby area at the cost of $10–$15 per ton. Around 6 acres of land was being cultivated using the biogas based power generated from the MOW that was being used for growing vegetables and maize.

DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications

In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.