Postdeposition Annealing In N2 Research Articles

(Invited) Consideration on Gate Stack Formation Processes of Ultrawide Bandgap Ga2O3 with SiO2 Dielectric Layer

MOSFETs on β-Ga2O3 are expected to be a high-efficient and cost-effective alternative option of high-voltage power devices. Taking account of the reliability and the large conduction-band offset against β-Ga2O3, it would be reasonable to employ SiO2 as the gate dieletric. In this study we investigated the effects of post-deposition annealing (PDA) on SiO2/β-Ga2O3 MOS gate stacks, in terms of the MOS electrical characteristics and the band alignment.β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution, and SiO2 films were deposited by electron-beam (EB) evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA at various temperatures from 600 to 1000℃ in either O2 or N2 ambient. Au was evaporated as gate electrode to form MOS capacitors. X-ray photoelectron spectroscopy (XPS) was conducted on the stacks with ~3nm-thick SiO2 for the evaluation of band alignment. Ultraviolet photoelectron spectroscopy (UPS) was also employed to determine the band diagram of β-Ga2O3 (001).Nearly-ideal capacitance-voltage characteristics were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The interface state density (Dit) determined by conductance method decreased down to ~1010 cm-3 at the energy level of EC−0.2 eV by PDA at higher temperature. The hysteresis width (ΔVhys) of C-V curves was smaller for the samples annealed at higher temperatures. The flatband voltage (VFB) shift after O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, suggesting that fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which indicates the formation of positive fixed charges in the stack. The beneficial influences of O2-PDA on those characteristics suggest that an oxygen deficiency introduced near the interface is one of the origins of interface defect states. It is noteworthy that Ga3d XPS on the surface of Ga2O3 substrate always shows a tailing in lower binding energy side, which is indicating oxygen deficiency on the surface. The intensity of this lower-binding-energy component reduced significantly when a bare-Ga2O3 substate was annealed in O2, however, it did not decrease efficiently even after O2-PDA when the surface was covered with SiO2. This is probably due to the oxygen rearrangement at SiO2/Ga2O3 interface determined by the difference of material properties of those oxides. This fact suggests that the Ga2O3 surface easily forms oxygen vacancies when it is covered with SiO2. This would be the reason why the formation of interface defect states is not suppressed without O2-PDA.Next the band diagram of β-Ga2O3 (001) substrate was investigated by UPS analysis where the energy level of valence band edge referring to the vacuum level was evaluted from the energy difference between minimum (cut-off) and maximum edges of the obtained kinetic energy spectra of photoelectrons. As a result we found the valence band edge of of β-Ga2O3 (001) was ~8.2 eV below the vacuum level, where the influences of O2 annealing at 1000℃ on the valence band edge energy level was limited to the shift within ~0.1eV. This would tell us the valence band offset between SiO2 and Ga2O3 should be around ~1.1eV, and the conduction band offset between them is to be around 2.8-2.9eV, by taking account of the well-reported SiO2 band diagram and assuming the bandgap of β-Ga2O3 as 4.7eV. On the other hand, the valence band offset estimated from the deconvolution of the XPS valence band spectrum for a ~3nm-thick SiO2/β-Ga2O3 stack from the energy edge difference between the deconvoluted spectra corresponding to SiO2 and Ga2O3, was a few hundreds of mV smaller than the above expected value (~1.1eV). This discrepancy is indicating the formation of an interface dipole layer between SiO2 and Ga2O3 with a pair of nagative and positive charges aligned at the interface to cause a shift in the band alignment. The magnitude of such dipole was indicated to be more significant (~0.5eV) for the stack after PDA at 1000℃, whereas it was less (0.2~0.3eV) after PDA at 600℃.In conclusion, we demonstrated that SiO2/β-Ga2O3 (001) MOS capacitors showed nearly-ideal electrical characteristics with significantly reduced interface defect density and small fixed charge density by applying O2-PDA. The band alignment of SiO2/β-Ga2O3 (001) MOS stack was clarified by photoelectron spectroscopy to confirm a very large conduction band offset of the stack, but an influence of the formation of interface dipole layer between SiO2 and Ga2O3 on the band alighment was also indicated.

Microstructure and optical properties of sputter-deposited Ga2O3 films

We report on the properties of gallium oxide (Ga2O3) thin films deposited on c-plane sapphire substrates using radio frequency magnetron sputtering under various conditions. The parameters varied included the composition of the deposition gas, the substrate temperature, and postdeposition annealing temperature. The optical characteristics obtained by UV-VIS spectroscopy showed excellent transparency of 90%–95% for all the films obtained. The structural and compositional properties of the films were determined using x-ray diffraction and energy dispersive spectrometry measurements. The films deposited in Ar at 400 °C showed diffraction peaks at 18.6°, 37.2°, and 58.2°, which are attributed to diffraction peaks from (2¯01), (4¯02), and (6¯03) planes of β-Ga2O3. Postdeposition annealing in N2 at 400–900 °C did not make any improvement in the crystalline quality of the films. The addition of tin in the films produced transparent films whose optical bandgaps decreased with increasing tin concentration in the films.

Impact of Surface Treatments and Post-Deposition Annealing Upon Interfacial Property of ALD-Al₂O₃ on a-Plane GaN

Optimization of interface characteristics between dielectric and non-polar GaN surface is very important and urgent for vertical GaN MOS device whose channel is perpendicular to the conventional cplane. In this work, the effects of piranha cleaning and N2 post deposition annealing (PDA) to the interface between atomic-layer-deposited (ALD)-Al 2 O 3 and a-plane GaN samples were comprehensively investigated by X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and photo-assisted capacitance-voltage (C-V) measurements. The piranha cleaning and N2 annealing can improve interface characteristics through the reduction in surface roughness and Ga-O bonds, respectively. Therefore, the frequency dispersion and hysteresis are nearly suppressed with a low interface trap quantity (Qit) of 4.1 x 10 11 cm -2 and a low average interface state density (Dit) of 2.04 x 10 11 cm -2 ·eV -1 from photoassisted C-V measurements, showing the great promise of utilizing piranha pretreatment, buffered oxide etch (BOE) dip, and N 2 annealing as an effective route to improve the vertical GaN MOS interface properties.

Study on the Effects of Post-Deposition Annealing on SiO2/β-Ga2O3 MOS Characteristics

MOSFETs on β-Ga2O3 is a new candidate of high-efficient and cost-effective alternative option for high-voltage power devices. In various studies, ALD-deposited Al2O3 films have been often employed as the gate dielectrics, however, it would be reasonable to replace with SiO2 if one considers the conduction-band offset against β-Ga2O3, which is limited to 1.5−1.6 eV [1] for Al2O3 but can be beyond 2 eV for the case of SiO2. In this study we investigated the effects of post-deposition-annealing (PDA) on the characteristics of SiO2/β-Ga2O3 MOS interface, especially focusing of the impact of the annealing temperature and ambient. β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution. Then SiO2 films were deposited by electron-beam evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by PDA in 1 atm-O2 at various temperatures from 600 to 1000℃. Au was evaporated as gate electrode to form MOS capacitors. For some samples an additional annealing at 400℃ was conducted in various ambient (O2, N2, and diluted H2). Nearly-ideal C-V characteristics with negligible hysteresis were obtained for the MOS capacitor fabricated with O2-PDA at 1000℃. The suppressed frequency dispersion indicates a successful formation of MOS interface with low interface defect densty. The energy profiles of interface state density (Dit) were determined by conductance method for the samples with different PDA conditions. Lower Dit was achieved for higher PDA temperatures, down to ~1010 cm-3 at the energy level of EC−0.2 eV. These values are significantly lower than typically reported ones so far on β-Ga2O3 [2, 3]. When we see the hysteresis width (ΔVhys) of C-V curves, defined by the difference between the voltages to observe the flatband-capacitance, the smaller ΔVhys was observed for the samples annealed at higher temperatures. The additional annealing at low temperature at 400℃ works for further reduction of ΔVhys to less than 1 mV/nm, irrespective of the annealing ambient, O2, N2, or diluted H2. After such low-temperature annealing at 400℃, I-V characteristics clarifed that these stacks resulted in the dielectric breakdown fields around 7−8 MV/cm, even though the process has not been optimized for the suppression of the leakage current. Next the flatband voltage (VFB) shift was compared for the samples annealed in different conditions. As we expected, O2-PDA resulted in VFB close to the ideal value estimated from the physical properties of Au and Ga2O3, probably because the fixed charge density at the interface would be minimized. However, PDA in N2 at 1000℃ resulted in a negative shift of VFB, which shows the introduction of positive fixed charges in the stack. The additional annealing in diluted H2 at 400℃ was also induced a negative VFB shift, whereas such additional annealing at the same temperature in O2 or N2 does not cause a significant shift. From these results it was suggested that oxygen deficiency introduction near the interface will induce positive fixed charges. Acknowledgement: This work was partly done in collaboration with JST, Center for Low Carbon Society Strategy.

Experimental Investigation of Remote Coulomb Scattering on Mobility Degradation of Ge pMOSFET by Various PDA Ambiences

The impact of various postdeposition annealing (PDA) ambiences (N2, O2, and NH3) on the hole mobility of germanium (Ge) pMOSFET with GeO2/Al2O3 gate-stack is investigated. It is found that the mobility is about 10% higher after N2 PDA, while it is about 10% smaller after O2 and NH3 PDA than that without PDA. The physical origin is attributed to the remote Coulomb scattering. The Ge/GeO2 interface charge Q1 decreases, but the GeO2/Al2O3 interface dipole Qdipole increases after PDA in N2, O2, and NH3. The higher mobility after N2 PDA is due to a smaller Q1 and Qdipole, while the lower mobility after O2 and NH3 PDA is due to a larger Qdipole. All these three PDA ambiences are beneficial to reduce the gate leakage current. Therefore, PDA in N2 is a balance approach for both the hole mobility improvement and gate leakage current reduction.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1−x as potential gate dielectrics for GaN/AlxGa1−xN/GaN high electron mobility transistors

This paper describes a method to optimally combine wide band gap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. (Ta2O5)x(Al2O3)1−x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped AlxGa1−xN/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta2O5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al2O3 to 4.6 eV for pure Ta2O5. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al2O3 up to 25.6 for Ta2O5. The effect of post-deposition annealing in N2 at 600 °C on the interfacial properties of undoped Al2O3 and Ta-doped (Ta2O5)0.12(Al2O3)0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al2O3/GaN-HEMT and (Ta2O5)0.16(Al2O3)0.84/GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al2O3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

Al2O3-TiO2 Nanolaminates for Conductive Silicon Surface Passivation

Al2O3-TiO2 nanolaminates are very attractive candidates for future conductive passivation layers because they are purely based on dielectric materials, which allow a simple integration in the state-of-the-art manufacturing process. In this study, Al2O3-TiO2 double and multilayers are grown by atomic layer deposition and systematically investigated. The nanolaminates feature good silicon surface passivation and moderate electrical conductivity. The best performance is found for a double-layer stack consisting of a 5 nm Al2O3 interface layer and a 15 nm TiO2 capping layer after postdeposition annealing in N2 or forming gas. With this stack, a surface recombination velocity of 15 cm/s and a contact resistance of 20 Ω·cm2 are achieved. In Al2O3 -TiO2 nanolaminates, the electrical transport is strongly influenced by the interaction of TiO2 and Al2O3 during layer growth. Raman measurements reveal that high conductivity correlates with a phase transition of TiO2 from amorphous to anatase.

Post Deposition Annealing Atmosphere Effect on SSI-LEDs Made of Zr-Doped HfO2 High-k Gate Dielectric

Recently, Kuo’s group proposed a new type of solid state incandescent light emitting device (SSI-LED) that has a simple MOS structure and emits the warm white light. This kind of device contains a high-k dielectric gate dielectric thin film, such as Zr-doped HfO2 (ZrHfO) or the HfOx [1-3]. The light emission is due to the thermal excitation of many nano-size conductive paths formed from the dielectric breakdown process when the applied gate voltage (Vg ) is above a breakdown voltage (VBD ). The post deposition annealing (PDA) step is critical to the MOS device performance because it affects the defect structures and densities in the high-k stack [4]. In this study, authors investigated the electrical and optical characteristics of the SSI-LED made of ZrHfO high-k films under different PDA atmospheres. The ZrHfO high-k films were sputter deposited on the p-type Si (100) (1015 cm-3) wafer using the one pump down process without breakdown the vacuum. The ZrHfO film was deposited from a ZrHf (12/88 wt. %) target in Ar/O2 (1:1) at 5 mTorr and 60 W for 12 min. After deposition, the sample was annealed at 800 °C in N2 or O2 for 3 min. An ITO layer was deposited on the high-k stack and etched into 300 µm dots as the gate electrodes. The backside of the wafer was sputter deposited with an aluminum layer for the ohmic contact purpose. The complete sample was annealed at 400 °C in forming gas for 5 min. The complete sample was characterized for electrical and optical properties. Figure 1 shows the I -V curves of the N2 PDA and O2 PDA devices with Vg swept from 0 to -10 V. The devices break abruptly at -5.65 V for the N2 PDA sample and -6.1 V for the O2 PDA sample. The O2 PDA sample has a larger physical thickness than that of the N2 PDA sample, e.g., the equivalent oxide thickness (EOT) of the former is 12.03 nm and that of the latter is 11.12 nm, which can explain the difference of the VBD ’s. In addition, the breakdown strength of the ZrHfO stack is related to the defect densities in the bulk high-k film and the Si/high-k interface layer [5]. The oxide trapping density (Qot ) and the interface density of states (Dit ) of the O2 PDA sample are 5.21×109 cm-2 and 1.61×1011 cm-2∙eV-1, separately, which are smaller than those of the N2 PDA sample, i.e., 7.13×109 cm-2 and 1.80×1011 cm-2∙eV-1, separately, which also favors of high VBD of the former sample. Figure 2 shows the high magnification light emission photos of the N2 PDA and O2 PDA devices stressed at Vg = -50 V. Both photos show that the light is emitted from many discrete bright dots uniformly distributed across the gate electrode. The N2 PDA sample contains a larger number of weaker dots than the O2 PDA sample does. Since the bright dots are from the thermal excitation of conductive paths in the sample, the number density of the bright dots is related to the breakdown strength of the sample. The O2 PDA sample has lower defect densities in the bulk ZrHfO and HfSiOx interface layers than the N2 PDA sample [5]. In addition, bright dots in Fig. 2(b) appear to be larger than most of those in Fig. 2(a). The bright dots at the edge of the sample appear to be larger than those in the center. The difference in the size distribution of the bright dots is related to the breakdown strength the high-k stack. Figure 3 shows the emission spectra of the N2 PDA and O2 PDA samples stressed at Vg = -50 V. Both spectra cover the same wavelength range including the visible and some of the near IR lights. The O2 PDA sample has a higher light intensity than the O2 PDA sample has, which is consistent with the result of Fig. 2. The peak wavelengths of both samples are very close, i.e., 681.5 nm for the O2 PDA sample and 682.0 nm for the N2 PDA sample. The similar composition of the conductive paths in both samples may be the cause of the spectrum shape. [1] Y. Kuo and C.-C. Lin, APL, 102, 031117 (2013). [2] Y. Kuo and C.-C. Lin, ESSL, 2, Q59 (2013). [3] Y. Kuo and C.-C. Lin, SSE, 89, 120 (2013). [4] G. D. Wilk, R. M. Wallace, and J. M. Anthony, JAP, 87, 484 (2000). [5] C.-C. Lin and Y. Kuo, E JSSST, 3,Q182 (2014). Figure 1

Chemical Nature and Control of High-k Dielectric/III-V Interfaces

III-V semiconductor surfaces are notoriously difficult to control as their native oxides are not stable. For the growth of high-k dielectric, interface passivation layers have recently been incorporated into InP/high-k dielectric stacks using different approaches, including atomic layer deposition (ALD) to grow thin aluminum silicate layers and deposition of a buffer silicon layer prior to aluminum oxide growth. While beneficial effects have been observed on the interface electrical properties, little is known about the chemical composition and formation mechanisms of these interfacial layers. Futhermore, there is growing evidence that elemental diffusion from the substrate or its oxide may impair electrical properties. There is therefore a need for chemical characterization of surfaces and interfaces under typical processing conditions. Combined in-situ IR measurements and ab initio calculations of InP(100) surfaces reveal that a mild annealing (~300oC) typically needed for atomic layer deposition leads to marked chemical changes at the surface, with the formation of surface InPO4-species (P=O and P-OH species). The initial interaction of trimethylaluminum with this hydrophosphonated surface is characterized by the formation of P-O-Al and dative bonding between Al and the oxygen atom of neighboring P=O moiety, requiring several cycles to complete this interfacial layer. This chemical interface transformation and subsequent impact on the quality of an ALD-grown Al2O3 layer can be substantially altered by silicon deposition using trisilane exposure. Comparison of several silicon precursors [SiCl4, Si(OCH3)4 and Si3H6] by in-situ spectroscopy reveals that Si3H6 best reacts with the hydrophosphonate-terminated surface and reduces the native oxide by forming a SiOx layer that prevents interaction of TMA with the native oxide, leading to a denser Al2O3 layer. Deposition of a thin aluminum silicate barrier layer by ALD is also investigated, and Al from TMA found to play a key role in activating silicon precursors. However, TMA reaction with Si-modified surfaces leads to efficient methyl transfer to Si, a source of interfacial carbon contamination. Finally, mass transport is examined in HfO2/In0.53Ga0.47As stacks. Diffusion of indium through HfO2 is observed after post deposition annealing in N2 or forming gas environments by low energy ion scattering and X-ray photo electron spectroscopy, and found to be consistent with changes in interface layer thickness observed by transmission electron microscopy. Prior to post processing, elemental arsenic is detected in the form of arsenic oxide at the surface of ALD-grown HfO2 and is desorbed upon annealing at 350oC. Indium diffusion occurring upon annealing, resulting in a reduction of the interfacial layer thickness and a potential densification of HfO2, is confirmed by an increase in capacitance.

Diffusion of In0.53Ga0.47As elements through hafnium oxide during post deposition annealing

Diffusion of indium through HfO2 after post deposition annealing in N2 or forming gas environments is observed in HfO2/In0.53Ga0.47As stacks by low energy ion scattering and X-ray photo electron spectroscopy and found to be consistent with changes in interface layer thickness observed by transmission electron microscopy. Prior to post processing, arsenic oxide is detected at the surface of atomic layer deposition-grown HfO2 and is desorbed upon annealing at 350 °C. Reduction of the interfacial layer thickness and potential densification of HfO2, resulting from indium diffusion upon annealing, is confirmed by an increase in capacitance.

Aluminum Oxide Deposited by Pulsed-DC Reactive Sputtering for Crystalline Silicon Surface Passivation

In this paper, we report on the surface passivation of crystalline silicon (c-Si) by pulsed-dc (p-dc) reactive-sputtered aluminum oxide (AlOx) films. For the activation of surface passivation, the films were subjected to post deposition annealing (PDA) in different ambients namely N2, N2 + O2, and forming gas (FG) in the temperature range of 420-520°C. The surface passivation was quantified by surface recombination velocity, which was correlated to the interface states at the silicon-dielectric interface and fixed charges in the dielectric. A good quality surface passivation with effective surface recombination velocity Seff of 41 cm · s-1 is obtained for PDA in N2 or N2 + O2 gas ambient. PDA in FG ambient at high temperature is found to degrade the passivation. The AlOx film annealed in FG ambient shows poorer thermal stability as compared with films annealed in the other two ambients. A clear path for further improvements in surface passivation quality of p-dc reactive sputter-deposited AlOx is suggested based on cross-sectional transmission electron microscopy and X-ray photoelectron spectroscopy analysis and electrical data.

Electrical properties of platinum interconnects deposited by electron beam induced deposition of the carbon-free precursor, Pt(PF3)4

Comprehensive analysis of the electrical properties, structure and composition of Pt interconnects, developed via mask-less, electron beam induced deposition of the carbon-free Pt precursor, Pt(PF3)4, is presented. The results demonstrate significantly improved electrical performance in comparison with that generated from the standard organometallic precursor, (CH3)3Pt(CpCH3). In particular, the Pt interconnects exhibited perfect ohmic behavior and resistivity that can be diminished to 0.24 × 10−3 Ω cm, which is only one order of magnitude higher than bulk Pt, in comparison to 0.2 Ω cm for the standard carbon-containing interconnects. A maximum current density of 1.87 × 107 A cm−2 was achieved for the carbon-free Pt, compared to 9.44 × 105 A cm−2 for the standard Pt precursor. The enhanced electrical properties of the as-deposited materials can be explained by the absence of large amounts of carbon impurities, and their further improvement by postdeposition annealing in N2. In-situ TEM heating experiments confirmed that the annealing step induces sintering of the Pt nanocrystals and improved crystallinity, which contributes to the enhanced electrical performance. Alternative annealing under reducing conditions resulted in improved performance of the standard Pt interconnects, while the carbon-free deposit suffered electrical and structural breakage due to formation of larger Pt islands.

Effects of high-temperature O2 annealing on Al2O3 blocking layer and Al2O3/Si3N4 interface for MANOS structures

In this paper, we have investigated the effects of O2 post-deposition annealing (PDA) on metal/Al2O3/Si3N4/SiO2/Si (MANOS) devices. Compared with low-energy plasma oxygen pre-treatment and the N2 PDA process, the O2 PDA process can lead to a significant retention improvement. The improvement is attributed to the removal of oxygen vacancies in Al2O3 block oxide and the oxygen incorporation at the Si3N4/Al2O3 interfacial layer which is determined by x-ray photoelectron spectroscopy (XPS) depth profiling and electrical characteristics. Metal/Al2O3/SiO2/Si (MAOS) devices are also studied to confirm these effects. As a result, we consider that the O2 PDA process is a crucial process for future MANOS-type memory devices.

Energy and Spatial Distributions of Electron Traps Throughout $\hbox{SiO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}$ Stacks as the IPD in Flash Memory Application

SiO2/high-? dielectric stacks will soon replace the conventional SiO2-based dielectric stacks in flash memory cells, as the thickness of SiO2 -based stacks is approaching its fundamental limit. The electron trap density in high-? layers is orders of magnitude higher than that in SiO2, which may introduce excessive leakage via trap-assisted tunneling current and become the limiting factor for the retention of memory cells. Understanding the properties of electron traps throughout the dielectric stack is essential for estimating the leakage current and for selecting materials and processes in order to reduce the leakage. However, detailed information on trap properties in the bulk of high-? layers is still missing. A recently developed two-pulse C-V measurement technique is used in this paper to investigate the energy and spatial distribution of electron traps throughout the SiO2/Al2O3 dielectric stacks. Four energy regions of electron traps have been observed. The shallower traps mainly above the Si conduction band bottom E CB are found distributed across the Al2O3 layer. A narrow band of traps below Si E CB with a bandwidth of about 0.1 eV can be observed near the SiO2/Al2O3 interface. Traps in the midlevel region corresponding to Si bandgap and traps in the deeper energy region mainly below Si valence band top are also observed. The postdeposition annealing in N2 has different impacts on the electron traps in different energy regions.

Annealing-temperature Dependence of Compositional Depth Profiles and Chemical Bonding States of CeOx/LaOx/Si and LaOx/CeOx/Si Structure

We have investigated the influence of post deposition annealing (PDA) on compositional depth profiles and chemical structures of CeOx/LaOx/Si(100) and LaOx/CeOx/Si(100) interfaces by angle-resolved X-ray photoemission spectroscopy. Analyses of Ce 3d and O 1s spectra show that a Ce oxidation state changes from Ce4+ to Ce3+ by PDA in N2 at and above 500{degree sign}C and changes from Ce3+ to Ce4+ by PDA in O2 at 300{degree sign}C. This implies that a Ce oxidation state can be controlled by changing the condition of PDA. The diffusion of Ce and La atom occurs at CeOx/LaOx interface by PDA above 500{degree sign}C.

Relationships among equivalent oxide thickness, nanochemistry, and nanostructure in atomic layer chemical-vapor-deposited Hf–O films on Si

The relationships among the equivalent oxide thickness (EOT), nanochemistry, and nanostructure of atomic layer chemical-vapor-deposited (ALCVD) Hf–O-based films, with oxide and nitrided oxide interlayers on Si substrates, were studied using x-ray photoelectron spectroscopy (XPS), high-resolution transmission electron microscopy (HRTEM), scanning transmission electron microscopy (STEM) in annular dark-field imaging (ADF), and parallel electron energy-loss spectroscopy (PEELS), capacitance–voltage, and leakage-current–voltage measurements. The XPS (Hf 4f binding energy shift) studies indicated the formation of Hf–O–Si bonds in as-deposited amorphous films, the amount of which was influenced by the interlayer composition and annealing conditions. After post-deposition annealing in N2 and O2, the Hf–O layers were nanocrystalline. Although HRTEM images showed a structurally sharp interface between the Hf–O layer and the interlayer, angle-resolved XPS, ADF imaging, and PEELS in the STEM revealed a chemically diffused HfSiOx region in between. This interdiffusion was observed by the detection of Si (using Si L edge) and Hf (using Hf O2,3 edge) in the Hf–O layer and the interlayer. For an annealed Hf–O/interlayer stack, with an ALCVD target thickness of 4.0 nm for the Hf–O layer on 1.2 nm of nitrided chemical oxide, the experimentally measured EOT and leakage current (at −1 V) were 1.52 nm and ∼10−8 A/cm2. A three-layer (1.2 nm interlayer of nitrided chemical oxide/compositionally graded, 2 nm region of HfSiOx/2 nm HfO2 layer) capacitor model was used to determine the respective contributions to the measured EOT, and the dielectric permittivity of the interlayer was found to be 6.06. These studies clearly indicate that a total EOT of 1 nm and below is attainable in the Hf–N–O–Si/Si–N–O system.

Hafnium oxide gate stack prepared by in situ rapid thermal chemical vapor deposition process for advanced gate dielectrics

A high-quality HfO2 gate stack with equivalent oxide thickness (EOT) of 7.8 Å and a leakage current of Jg=0.5 mA/cm2 @ Vg=−1.0 V has been achieved by an in situ rapid thermal chemical vapor deposition process. It is found that both NH3-based interface layer and N2 postdeposition annealing are very effective in reducing EOT and leakage, and at the same time, improving film qualities. These HfO2 gate stacks show negligible frequency dependence, small hysteresis in capacitance–voltage (C–V) and weak temperature dependence of the leakage current. They also show negligible charge trapping at high voltage stress.

Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from a Ta(OC2H5)5 precursor

In this work, the structural and electrical properties of amorphous and crystalline Ta2O5 thin films deposited on p-type Si substrates by low-pressure chemical vapor deposition from a Ta(OC2H5)5 precursor have been investigated. The as-deposited layers are amorphous, whereas crystalline Ta2O5 was obtained after postdeposition O2 treatment at 800 °C. As evidenced by x-ray diffraction, a hexagonal structure was obtained in the latter case. Physicochemical analysis of our layers shows that the O2-annealing step leads to the growth of a thin (∼1 nm) interfacial SiO2 layer but was not sufficient to reduce the level of hydrocarbon contamination. The dominant conduction mechanism in amorphous Ta2O5 is clearly due to the Poole–Frenkel effect, whereas the situation remains unclear for crystalline Ta2O5 for which no simple law can be invoked to correctly describe its conduction properties. From capacitance–voltage measurements, the dielectric constant was found to be ∼25 for amorphous samples, but values ranging from 56–59 were found for crystalline layers, suggesting a particularly high anisotropic character of the crystalline phase. Finally, the effects of postdeposition annealing in N2 and forming gas at 425 °C have been investigated for both types of films.

Effects of native oxide removal from silicon substrate and annealing on SiO2 films deposited at 120 °C by plasma enhanced chemical vapor deposition using disilane and nitrous oxide

The effects of native oxide removal from the Si substrate surface and annealing on SiO2 films deposited by plasma enhanced chemical vapor deposition at 120 °C using Si2H6 and N2O are investigated. The effective oxide charge and the interface trap densities for the as-deposited films with the native oxide etched off the substrate surface prior to the film deposition were nearly five times higher than for the as-deposited films without the removal of the native oxide. Postdeposition annealing in N2 reduced the effective oxide charges for the films deposited on substrates without the native oxide. However, a 30 min postmetallization anneal at 400 °C in 5% H2 in N2 ambient reduced both the effective oxide charge density and the interface trap density much more effectively. The values for both these charge densities and the dielectric breakdown field were comparable after this postmetallization annealing regardless of the substrate cleaning procedure and the postdeposition annealing cycle in N2.

Cadmium selenide thin-film transistors

Vacuum-deposited CdSe thin-film transistors (TFT’s) with reproducible good stability, performance, uniformity, and yield were made using sputtered SiO2 gate insulator, Cr source–drain (s–d) electrodes, and postdeposition annealing in N2. These materials and procedures permit the use of multiple pumpdown fabrication methods with no loss in ac characteristics and little sacrifice in dc stability. Promising results were obtained using photolithography (PL) to delineate s–d electrodes, further simplifying fabrication. The dc instability is electron-trapping type and the drain current decay exhibits a logarithmic time dependence. The slope of this decay curve is used as a parameter to describe device stability and its dependence on the fabrication methods studied: M=0.03–0.06 for one-pumpdown devices, 0.05–0.08 for multiple pumpdown TFT’s, and 0.1–0.2 for TFT’s with PL-delineated s–d electrodes. Preliminary reliability studies show that suitably encapsulated TFT’s have long time stability comparable to the good short time stability observed for fresh devices, indicating the absence of built-in failure mechanisms and the capability for a satisfactory operating life.