Positive Polarity Reed-Muller Research Articles

Multi-level Attack with Dynamic S-box Variable key Pattern Generation for Key Cohort Using AES

In recent times, data transmission in electronic medium is found to be more susceptible to several attacks. The study aims to control the multi-level attacks in encryption and decryption process by using Advanced Encryption Standard (AES) algorithm based S box operations. In AES based variable key generation pattern, every round generates the new key. The generation of multiple keys strengthen the operation of AES-dynamic S box. The AES algorithm performs operation on a 128 bit plain text and utilizes identical key for decryption and encryption process. The proposed algorithm shows significant improvements in the quality of encryption and decryption. The performance of the proposed system has been analysed in accordance with delay, power consumption and number of slices. Further the efficiency of the proposed system has been compared with other existing methods such as Positive Polarity Reed Muller (PPRM), Modified Positive Polarity Reed Muller (MPPRM) Twisted Binary Decision Diagram (TBDD) and Composite Field (CF) architecture. The results exposed that the proposed system outperforms with superior performance.

Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems

The hardware footprint for S-box specification in lightweight block cipher as appropriate to IoT and CPS information security systems is presented in this paper. The S-box Boolean function in the lightweight block cipher is defined using the Reed-Muller structure. A Rule Based–Common Sub-structure Sharing Optimization (RB-CSSO) algorithm has been proposed towards improving the performance efficiency of Reed-Muller structure. This novel hybrid RB-CSSO optimization mechanism first transforms the direct Positive Polarity Reed Muller (PPRM) S-box representation into Mixed Polarity Reed-Muller (MPRM) S-box architecture using local rule based transformation. Secondly, the Common Sub Term (CST) and Common Sub-expression (CSE) merging/elimination are employed over the resulting MPRM structure. The combined rule-based transformation and the common sub-function sharing demonstrate an overall reduction in area, delay and power of the Reed-Muller S-box structure. Both the theoretical analysis and the experimental verification demonstrate reduction in area and delay of S-box. Post synthesis results based on ASIC standard cell based implementations have been used to analyze area, delay and power values across Process, Voltage and Temperature (PVT) corners for a wide range of operating conditions. Extensive comparisons between direct PPRM and optimized MPRM implementations have been carried out. The post layout simulations of S-box structures realized show the advantages of lower area-delay product, power-area product and power-delay product. This work thus authenticates the application of proposed structure for lightweight, resource constrained security systems. Industry standard full suite of Cadence® tools have been employed in the simulations using 65 nm TCBN65GPLUS standard cells of TSMC technology library.

EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card

The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identification (RFID) and smart cards that are energy-efficient and secure against Differential Power Analysis (DPA) attacks. Adiabatic logic is one of the circuit design techniques that can be used to design energy-efficient and secure hardware. However, the existing DPA resistant adiabatic logic families suffer from non-adiabatic energy loss. Therefore, this work presents a novel adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) family that reduces the non-adiabatic energy loss and also is secure against DPA attacks. The proposed EE-SPFAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on EE-SPFAL are used to implement a Positive Polarity Reed Muller (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that EE-SPFAL based S-box circuit saves up to 65 percent of energy and 90 percent of energy per cycle as compared to the S-box circuit implemented using existing Secured Quasi-Adiabatic Logic (SQAL) and conventional CMOS logic, respectively. Further, the security of EE-SPFAL based S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the EE-SPFAL based S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, we have implemented the one round of Advanced Standard Encryption (AES) algorithm and we found that one round of EE-SPFAL logic based AES consumes uniform current with different input plain texts. Low energy consumption and security against DPA attacks makes EE-SPFAL logic a suitable candidate to implement in IoT devices such as RFID and smart cards.

Ultralow-Power and Secure S-Box Circuit Using FinFET Based ECRL Adiabatic Logic

Advanced Encryption Standard (AES) is the widely used technique in critical cyber security applications. In AES architecture S-box is the most important block. However, the power consumed by S-box is 75% of the total AES design. The S-box is also prone to Differential Power Analysis (DPA) attack which is one of the most threatening types of attacks in cryptographic systems. In this paper, a three-stage positive polarity Reed-Muller (PPRM) S-box is implemented with 45nm FinFET using Efficient Charge Recovery Logic (ECRL) to reduce power consumption. The simulation results indicate up to 66% power savings for FinFET based S-box as compared to CMOS design. Further, the FinFET ECRL 8-bit S-box circuit is evaluated for transitional energy fluctuations and peak current traces to compare its resistance against side-channel attacks. The lower energy variations and uniform current trace exhibit the improved security performance of the circuit to withstand DPA and Differential Electromagnetic Radiation Attacks (DEMA).

Efficient Three Variables Reversible Logic Synthesis Using Mixed-polarity Toffoli Gate

In this paper, we present an efficient reversible logic synthesis algorithm that uses Toffoli and mixed-polarity based Toffoli gate. In this paper, we propose an algorithm to synthesizereversible function in their positive-polarity Reed Muller (PPRM) expansion and usethe Hamming Distance (HD) approach to select suitable transformation path. Once a transformation path is defined, suitable gates for substitution are selected through the gate matching factor and reduction is performed. The algorithm does not generate any extra lines and thus keeping the synthesized function in its simplest form. The algorithm target on efficient way to synthesize three variables based reversible function into a cascade of Toffoli and mixed-polarity based Toffoli gate in term of quantum cost and gate count. Experimental results showthat the proposed algorithm is efficient in terms of the realization of all three variable based reversible functions.

A Fast Algorithm for Synthesis of Quantum Reversible Logic Circuits

Reversible logic finds many applications,especially in the area of quantum computing. Quantum reversible logic circuits are basic elements in quantum computer construction. Synthesis of quantum reversible logic circuits means to automatically construct desired quantum reversible logic circuit with minimal quantum cost. The authors absorb different ideas of reversible logic circuits synthesis and present a novel and efficient algorithm which can automatically derive the positive polarity Reed-Muller expansion (RM). A solution space tree is constructed to create quantum reversible logic circuits. Firstly,floor traversal is applied globally,and depth-first search is used locally. Secondly,according to the technique of template optimization,the bound function is constructed,which can rapidly prune the branches with no or nonoptimal result. Thirdly,factors of RM are first considered,therefore the algorithm can effectively construct optimal result and saves computational cost significantly. Judging by the internationally recognized reversible functions of three variables,the proposed algorithm not only synthesizes all optimal reversible functions,but also runs extremely faster than others of the same kind.

A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power consumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

EXOR transform of inputs to design efficient two-level AND/EXOR adders

An input transformation based on EXOR gates is presented which enables efficient two-level AND/EXOR representations of adders to be constructed. In general, adders only have exponential two-level representations, but by using the input transformation the complexity decreases to O(n2) requiring only a linear hardware overhead. Exclusive sum-of-products (ESOP) and positive polarity Reed-Muller expression (PPRM) circuits are considered.

Testability of 2-Level AND/EXOR Circuits

It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.

Algorithms for conversion of minterms to positive polarity Reed-Muller coefficients and vice versa

In this paper, an algorithm for mapping positive polarity Reed-Muller (PPRM) coefficients from canonical sum of products (CSOP) coefficients is presented. Another algorithm for mapping CSOP coefficients is also presented. Both algorithms are more space efficient than the existing algorithms.

Easily testable realizations for generalized Reed-Muller expressions

This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy (1972) and Saluja-Reddy's (1975) methods, and has the following features. The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The average number of products for GRMs is less than half of that for PPRMs, and is less than that of sum-of-products expressions (SOPs). The network consists of a literal part, an AND part, an EXOR part, and a check part. The EXOR part can be a tree instead of a cascade. Thus, the network is faster. The test detects multiple stuck at faults under the assumption that the faults occur at most one part, either the literal part, the AND part, the EXOR part, or the check part.

A semicustom IC for generating optimum generalized Reed-Muller expansions

The paper explains the theory and design of a semicustom integrated circuit (IC) for the generation of the optimum polarity of a given Boolean function. Given the minterm coefficients of a Boolean function, the chip computes the coefficients of all the fixed polarities of the generalized Reed-Muller expansions, and identifies the polarity with the least number of terms. The chip can also convert the coefficients of the positive polarity Reed-Muller expansion to a sum of products form. The design was completed using Mentor-Graphics VA.4 and the Mietec 0.7 μm CMOS Library.

Optimization of Reed-Muller logic functions

Two algorithms are presented, the first is a technique to determine good, though not necessarily optimum, fixed polarity Reed-Muller expansions of completely specified boolean functions. The second algorithm determines the allocations of the ‘don't care’ terms of incompletely specified boolean functions resulting in optimum positive polarity Reed-Muller expansions. Additionally, investigations are made into combining these two techniques to determine fixed polarity Reed-Muller expansions of incompletely specified boolean functions. Results are presented which show the effectiveness of the techniques and comparisons are made with existing methods.

Efficient and fast algorithm to generate minimal Reed-Muller Exclusive-OR expansions with mixed polarity for completely and incompletely specified functions and its computer implementation

In this paper a new, very fast, simple and computationally effective algorithm to generate the minimal Reed-Muller Exclusive OR (ExOR) expansion with mixed polarity for any arbitrary, completely and incompletely specified switching function. The major consideration of this algorithm is to obtain a minimum number of product terms in the ExOR function. The algorithm is based on the use of Boolean matrix representation and an efficient technique called “minterm separation operation” developed by the author. The proposed algorithm consists of three procedures: (1) removing the variables on which a given switching function does not depend; (2) generating the positive polarity Reed-Muller expansion coefficients; and then (3) generating the final Reed-Muller ExOR expansion with mixed polarity in the canonical product form directly. A procedure for handling incompletely specified functions to deduce the suitable selection of “Don't care” terms is combined with Procedure 1 and/or Procedure 2. The proposed algorithm can deal with functions of large number of variables because there is no restriction from the algorithm on the number of variables within any given function. Based on the proposed approach, a fast and efficient computer program is developed. This computer program accepts an arbitrary switching function in terms of minterms and returns a mixed-polarity Reed-Muller expansion as an output in its canonical product form. The realization of the developed algorithm and the computer implementation was tested on many examples from the literature as well as on many arithmetic functions. On all examples the solutions were either the same or better than those generated by other methods.