Positive Gate Bias Research Articles

Impact of post-deposition annealing on SiO2/SiC interfaces formed by plasma nitridation of the SiC surface and SiO2 deposition

Abstract We examined the impact of post-deposition annealing (PDA) on SiO2/SiC structures formed by plasma nitridation of the SiC surface followed by sputter deposition of SiO2. The interface state density near the conduction band edge of SiC was reduced from about 2×1012 to 1×1011 eV−1cm−2 as the CO2-PDA temperature increased from 1050 to 1250℃. In addition, the sample treated by CO2-PDA exhibited substantially higher immunity against positive gate bias stress than the standard NO nitridation. Our findings indicate that defect passivation by CO2-PDA plays a crucial role in improving the performance and reliability of SiC MOS devices formed by sputter-SiO2 deposition.

Al modification layer method for enhancing InAlZnO transistors

In this work, a surface engineering method is proposed to boost electrical performance and stability of the InAlZnO (IAZO) transistors, of which an Al modification layer is deposited on surface of the IAZO channel layer. Through analysed by transmission electron microscope and X-ray photoelectron spectroscopy, the IAZO thin film with Al modification layer undergoes a reduction reaction to generate more oxygen vacancies. Hall effects measurement further demonstrates that IAZO thin films with Al modification layer exhibit higher carrier concentrations than the ones without Al modification layer. The IAZO transistors with Al modification layer exhibit better performance and stability, including a field-effect mobility of 4.36 cm2 V−1s−1 (an improvement of about three-fold), a small subthreshold swing of 105.23 mV/decade, a high on-to-off current ratio greater than 107, and a threshold voltage shift of less than 0.50 V under positive and negative gate bias stress. Moreover, the IAZO transistors with Al modification layer demonstrate high thermal stability under 400 °C for 120 min in air atmosphere. Based on this method, the IAZO inverters have been implemented with high voltage gain of 87.55 V/V. This surface engineering technology paves the way for application of high-performance oxide transistors for advanced monolithic three-dimensional integration.

Recovery of drain-induced threshold voltage shift by positive gate bias in GaN power HEMTs with p-GaN gate

We demonstrate that exposure to positive gate bias can favor a fast recovery of the threshold voltage variation induced by off-state stress, in p-GaN gate high electron mobility transistors. Two process splits were investigated, having different Schottky barriers at the metal/p-GaN junction. Results indicate that: (a) drain stress may result in significant threshold voltage increase; (b) devices with sufficiently high gate leakage current show an immediate recovery after gate turn-on, resulting in stable operation in actual applications. The contribution of leakage current is demonstrated, based on recovery experiments at different voltages and for the same rate of hole injection from the gate.

Carrier Mobility Enhancement in Ultrathin-Body InGaAs-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Based on Dual-Gate Modulation

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al2O3 interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 1013 cm−2 was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field.

Amorphous InZnSnO thin-film-transistors performance enhancement with low-energy Xenon Pulsed-light annealing

The electrical characteristics and stability of amorphous indium-zinc-tin oxide (IZTO) thin-film transistors (TFTs) were significantly improved in this study using low-energy Xenon pulsed-light annealing (PLA). In comparison to conventional furnace annealing (FA), PLA treatment significantly reduced the processing temperature and annealing time. Besides, the defect states are obviously reduced from 1.73×1012 cm-2 to 6.53×1011 cm-2 by PLA treatment, resulting in improved device electrical characteristics and enhanced reliability, including improved carrier mobility from 20.08 to 39.61 cm2/V∙s, threshold voltage from 0.82 to 0.24 V, subthreshold swing (S.S.) from 0.54 to 0.24 V/decade, and the ON/OFF current ratio from 2.32×107 to 7.31×108. In addition, the enhanced stability is observed under both positive gate-bias stress (PGBS) of VGS = 30 V and negative gate-bias stress (NGBS) of VGS = –30 V for a stress duration of 3000 s. The threshold voltage shift (ΔVTH) is reduced from 8.31 V to 1.65 V and from –3.93 V to –1.51 V, respectively. This is the first time low-energy PLA was conducted for IZTO TFT performance improvement.

Reliable Operation in High-Mobility Indium Oxide Thin Film Transistors.

Transparent oxide semiconductors (TOSs) based thin-film transistors (TFTs) that exhibit higher field effect mobility (µFE) are highly required toward the realization of next-generation displays. Among numerous types of TOS-TFTs, In2O3-based TFTs are the front-running candidate because they exhibit the highest µFE ≈100cm2V-1s-1. However, the device operation of In2O3 TFTs is unreliable; a large voltage shift occurs especially when negative gate bias is applied due to adsorption/desorption of gas molecules. Although passivation of the TFTs is used to overcome such instability, previously proposed passivation materials do not improve the reliability. Here, it is shown that the In2O3 TFTs passivated with Y2O3 and Er2O3 films are highly reliable and do not show threshold voltage shifts when applying gate bias. Positive and negative gate bias is applied to the In2O3 TFTs passivated with various insulating oxides and found that only the In2O3 TFTs passivated with Y2O3 and Er2O3 films do not exhibit threshold voltage shifts. It is observed that only the Y2O3 grew heteroepitaxially on the In2O3 crystal. This is the origin of the high reliability of the In2O3 TFTs passivated with Y2O3 and Er2O3 films. This finding accelerates the development of next-generation displays using high-mobility In2O3 TFTs.

Enhancing the Stability and Mobility of TFTs via Indium-Tungsten Oxide and Zinc Oxide Engineered Heterojunction Channels Annealed in Oxygen Ambient.

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium-tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility.

High-mobility and high-reliability Zn-incorporated amorphous In2O3-based thin-film transistors

Polycrystalline indium oxide-based thin film transistors (In2O3 TFTs) have attracted considerable attention because of high field effect mobility (μ FE ∼ 100 cm2 V−1 s−1). However, In2O3 TFTs exhibit poor reliability owing to the adsorption and/or desorption of gas molecules at the grain boundaries. The incorporation of Zn suppresses the crystallization of In2O3. Herein, we systematically studied the effect of Zn incorporation into In2O3 TFTs. The crystallization of In2O3 was suppressed when the Zn concentration ranged from 25% to 68%. Amorphous InZnO (IZO) TFTs with 25% Zn exhibited the highest μ FE of 41 cm2 V−1 s−1 and excellent reliability. In contrast, polycrystalline IZO TFTs showed a low μ FE <12 cm2 V−1 s−1 due to the formation of grain boundaries, and poor reliability after positive gate bias, mostly due to electron trapping at the polycrystalline/insulator interface. These results render an approach to realize In2O3 TFTs that show reasonably high μ FE and excellent reliability.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

The impact of sputtering pressure on the TiO2/p-Si interface and its implications for hole-blocking and photodetection

One convenient approach to minimize the surface recombination loss in Si is to passivate the surface dangling bonds by depositing a thin TiO2 layer on the bulk Si. Besides, the p-Si/TiO2 interface can initiate hole-blocking and facilitate efficient electron transport through the TiO2 layer; thereby, promoting the extraction of electrons for efficient onward utilization. In this context, the current investigation involves studying how the Ti3+ donor states, produced by deliberately introducing O-vacancies controlled by changing the plasma pressure in the RF-magnetron sputtering chamber during the growth of the TiO2 thin films, can change the material's Fermi level and work function and modify the band bending and band offset as well as the fixed oxide charge density in the p-Si/TiO2 heterojunction interface. The TiO2/p-Si interface has been studied through capacitance-voltage (C-V) analysis to determine the interface parameters such as fixed oxide charge, the density of interface traps, and the dielectric constant of TiO2. The studied hole-blocking property of the interface has been correlated to the photoresponsivity of the metal-oxide-semiconductor (MOS) structure. The MOS device fabricated at a pressure of 30 mTorr displays a large saturation current (15.95 μA cm–2) when subjected to a positive gate bias, facilitated by the relatively low conduction band offset (ΔEC ∼0.20 eV), significant positive fixed oxide charge (+1.18 ×1011 cm–2) and the interface trap density (1.03 ×1012 cm–2), which enhanced the transport of minority carrier electrons from the p-Si to the metal, resulting in a good photo responsivity ∼0.158 AW–1 and photo gain of ∼37.5 under white light illumination. Optimum hole-blocking and surface passivation characteristics of the TiO2/p-Si interface together may facilitate fabricating improved heterojunction Si solar cells.

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

Improvement of the electrical properties of amorphous indium-gallium-zinc oxide thin-film transistors by cross-linked CYTOP passivation

In this study, we investigated the effect of a cross-linked CYTOP passivation layer on the electrical properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Cross-linked CYTOP passivation showed a deeper fluorine diffusion depth than CYTOP passivation owing to the chemical reaction between the cross-linking agent and IGZO layer. The cross-linking agent reduces the weakly bonded oxygen in the IGZO layer via a chemical reaction, enhancing fluorine diffusion into the IGZO layer. Therefore, the effect of fluorine on the IGZO layer was enhanced by using cross-linked CYTOP as a passivation layer. The diffused fluorine reduced the defect states by passivating the oxygen-related defects such as oxygen vacancies and weakly bonded oxygen and increased the carrier concentration by replacing metal–oxygen bonds with metal-fluorine bonds. IGZO TFTs with cross-linked CYTOP passivation exhibited a threshold voltage of −0.35 V, saturation mobility of 1.93 cm2/V∙s, and subthreshold swing of 0.53 V/dec. Using a cross-linked passivation layer also improved the reliability under positive gate bias stress. Consequently, a cross-linked CYTOP passivation layer can effectively improve the electrical properties of IGZO TFTs by incorporating fluorine atoms into the IGZO layer.

A Comparative Study on the Degradation Behaviors of Ferroelectric Gate GaN HEMT with PZT and PZT/Al2O3 Gate Stacks.

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O3 (PZT) and a composite PZT/Al2O3 bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al2O3 gate oxide. Owing to the large difference in dielectric constants between PZT and Al2O3, the strong electric field in the Al2O3 interlayer makes PZT/Al2O3 GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al2O3 interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal-insulator-semiconductor HEMT (MIS-HEMT).

Total X-ray dose effect on graphene field effect transistor

In this paper, the total dose effects of graphene field-effect transistors (GFETs) with different structures and sizes are studied. The irradiation experiments are carried out by using the 10-keV X-ray irradiation platform with a dose rate of 200 rad(Si)/s. Positive gate bias (&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;G&lt;/sub&gt; = +1 V, &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;D&lt;i&gt; &lt;/i&gt;&lt;/sub&gt;= &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;S&lt;i&gt; &lt;/i&gt;&lt;/sub&gt;= 0 V) is used during irradiation. Using a semiconductor parameter analyzer, the transfer characteristic curves of top-gate GFET and back-gate GFET are obtained before and after irradiation. At the same time, the degradation condition of the dirac voltage &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;Dirac&lt;/sub&gt; and the carrier mobility &lt;i&gt;μ&lt;/i&gt; are extracted from the transfer characteristic curve. The experimental results demonstrate that &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;Dirac&lt;/sub&gt; and carrier mobility &lt;i&gt;μ&lt;/i&gt; degrade with dose increasing. The depletion of &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;Dirac&lt;/sub&gt; and carrier mobility &lt;i&gt;μ&lt;/i&gt; are caused by the oxide trap charge generated in the gate oxygen layer during X-ray irradiation. Compared with the back-gate GFETs, the top-gate GFETs show more severely degrade &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;Dirac&lt;/sub&gt; and carrier mobility, therefore top-gate GFET is more sensitive to X-ray radiation at the same cumulative dose than back-gate GFET. The analysis shows that the degradation of top-gate GFET is mainly caused by the oxide trap charge. And in contrast to top-gate GFET, oxygen adsorption contributes to the irradiation process of back-gate GFET, which somewhat mitigates the effect of radiation damage. Furthermore, a comparison of electrical property deterioration of GFETs of varying sizes between the pre-irradiation and the post-irradiation is made. The back-gate GFET, which has a size of 50 μm×50 μm, and the top-gate GFET, which has a size of 200 μm×200 μm, are damaged most seriously. In the case of the top-gate GFET, the larger the radiation area, the more the generated oxide trap charges are and the more serious the damage. In contrast, the back-gate GFET has a larger oxygen adsorption area during irradiation and a more noticeable oxygen adsorption effect, which partially offsets the damage produced by irradiation. Finally, the oxide trap charge mechanism is simulated by using TCAD simulation tool. The TCAD simulation reveals that the trap charge at the interface between Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt; and graphene is mainly responsible for the degradation of top-gate GFET property, significantly affecting the investigation of the radiation effect and radiation reinforcement of GFETs.

Gate-readout and a 3D rectification effect for giant responsivity enhancement of asymmetric dual-grating-gate plasmonic terahertz detectors

Abstract We experimentally investigated the asymmetric dual-grating-gate plasmonic terahertz (THz) detector based on an InGaAs-channel high-electron-mobility transistor (HEMT) in the gate-readout configuration. Throughout the THz pulse detection measurement on the fabricated device, we discovered a new detection mechanism called the “3D rectification effect” at the positive gate bias application, which is a cooperative effect of the plasmonic nonlinearities in the channel with the diode nonlinearity in the heterobarrier between the InGaAs channel layer and the InAlAs spacer/carrier-supply/barrier layers, resulting in a giant enhancement of the detector responsivity. We also found that an undesired long-tail waveform observed on the temporal pulse photoresponse of the device is due to trapping of carriers to the donor levels in the silicon δ-doped carrier-supply layer when they tunnel through the barrier to the gate and can be eliminated completely by introducing the so-called inverted-HEMT structure. The internal current responsivity and noise-equivalent power are estimated to be 0.49 A/W (with the equivalent voltage responsivity of 4.9 kV/W with a high output impedance of 10 kΩ) and 196 pW/√Hz at 0.8 THz. These results pave the way towards the application of the plasmonic THz detectors to beyond-5G THz wireless communication systems.

Geometrically designed amorphous oxide semiconductor heterojunction thin-film transistors for enhanced electrical performance and stability

We report the geometrical design of indium-zinc-tin-oxide/zinc-tin-oxide (IZTO/TZO) heterojunction thin-film transistors (TFTs) to achieve high electrical performance and stability. The coverage ratio of the IZTO front-channel-layer (FCL) in the channel region was varied to investigate its impact on electrical properties such as field-effect mobility and bias stability. We observed that with a 90% coverage ratio of IZTO FCL, the mobility increased from 15.9 cm2 Vs−1 to 20.4 cm2 Vs−1, with a suppressed threshold voltage (V th) shift. The IZTO/ZTO TFTs exhibited improved positive gate-bias stability showing a V th shift of +2.46 V. The band bending occurring at the heterointerface is attributed to the enhanced electrical performance.

Improved reliability of a-IGZO thin-film transistor under positive gate bias stress by utilizing NH3 plasma treatment

In this paper, the degradation mechanisms of the bottom-gate amorphous InGaZnO thin film transistors (a-IGZO TFTs) under positive gate bias stress (PBS) are investigated. The PBS-induced degradation can be attributed to the electron capture at the interface of the gate insulator and a-IGZO and the generation of oxygen interstitial defects (Oi) in a-IGZO. The oxygen interstitial defect density (NOi) can be calculated by the degradation of SS during recovery after PBS. It is found that the proportion of degradation caused by Oi increases with the increased a-IGZO thickness. By utilizing NH3 plasma treatment, the threshold voltage shift was reduced by >40 % under PBS (@VG = 5 V, t = 1000s). Further analysis shows that NH3 plasma treatment can effectively suppress the electron capture at the interface and the generation of Oi during PBS. Thus, PBS reliability of a-IGZO TFTs is improved by the proposed method.

Trade-off between gate leakage current and threshold voltage stability in power HEMTs during ON-state and OFF-state stress

We present a detailed investigation of the impact of electron gate leakage on the threshold voltage stability of normally-off GaN HEMTs with p-GaN gate. The analysis is based on combined DC, pulsed and transient measurements, carried out on two test wafers with different gate processes, resulting in different levels of gate leakage current. The key results demonstrate: (a) the existence of four different charge-trapping processes, whose interplay determines the sign and amplitude of the threshold voltage variation; (b) a reasonable increase in gate leakage is beneficial for eliminating the negative threshold voltage instability under positive gate bias, and for substantially reducing the positive threshold shift under off-state stress. Furthermore, (c) we present a proper characterization methodology for device understanding.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Reduced Defect Density in MOCVD-Grown MoS2 by Manipulating the Precursor Phase.

Advancements in the synthesis of large-area, high-quality two-dimensional transition metal dichalcogenides such as MoS2 play a crucial role in the development of future electronic and optoelectronic devices. The presence of defects formed by sulfur vacancies in MoS2 results in low photoluminescence emission and imparts high n-type doping behavior, thus substantially affecting material quality. Herein, we report a new method in which single-phase (liquid) precursors are used for the metal-organic chemical vapor deposition (MOCVD) growth of a MoS2 film. Furthermore, we fabricated a high-performance photodetector (PD) and achieved improved photoresponsivity and faster photoresponse in the spectral range 405-637 nm compared to those of PDs fabricated by the conventional MOCVD method. In addition, the fabricated MoS2 thin film showed a threshold voltage shift in the positive gate bias direction owing to the reduced number of S vacancy defects in the MoS2 lattice. Thus, our method significantly improved the synthesis of monolayer MoS2 and can expand the application scope of high-quality, atomically thin materials in large-scale electronic and optoelectronic devices.