Positive Back Bias Research Articles

TCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Ω-Gate Nanowire MOS Transistors With Ultra-Thin BOX

This work presents an analysis of the application of active substrate bias (or back bias) on the charge transport properties of n-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\Omega }$ </tex-math></inline-formula> -gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width. Additionally, the influence of back bias on the electrical parameters of these devices is also investigated through DC parameters such as on-to-off-state current ratio and DIBL. The evaluation is conducted by 3D TCAD simulations calibrated with experimental data. The application of negative back bias on nMOS transistors not only shifts the threshold voltage, but also causes mobility degradation due to the negative potential on the channel pushing the charges against the gate oxide interface. On the other hand, when positive back bias is applied, despite the mobility improvement allowed by the back channel’s superior mobility and the front channel’s less compacted inversion layer, at higher substrate bias levels, a strong mobility degradation is observed in the back channel due to the substrate’s high electric field, resulting in reduction of the channel’s overall effective mobility. The application of positive substrate bias degrades the subthreshold slope, leading to smaller on-to-off-state current ratio, as well as the reduced control of channel charges by the gate electrode worsens the DIBL.

Study of the UTBB BESOI Tunnel-FET working as a Dual-Technology Transistor

In this work, we further investigate the operation of the BESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the struc-ture, but also as an nMOS when a positive back bias is ap-plied. The working principle is based on the generation of a channel of either holes or electrons by the back gate electric field, which can then be depleted through the front gate bias. TCAD device simulation was used for the proof of concept.

The total ionizing dose response of leading-edge FDSOI MOSFETs

In this paper, the total ionizing dose (TID) response of Ultra-Thin SOI (UTSOI) transistor is presented. TID experiments were performed on both NMOS and PMOS transistors under three different bias configurations (ON-state, OFF-state, TG-state). The results show that the OFF bias is relatively worse compared to other bias configurations for both NMOS and PMOS transistors. And the TID response variability caused by bias configuration during irradiation is small in UTSOI transistors. Besides this, the impact of back gate bias on TID response is also investigated. When a positive back bias is applied on NMOS transistor to achieve better performance, the threshold voltage degradation caused by TID becomes worse. While the negative back bias of PMOS transistor can lead to both better performance and higher TID tolerance. An explanation of back gate impact on front gate TID response is given with TCAD simulation.

Impact of Fin Width and Back Bias Under Hot Carrier Injection on Double-Gate FinFETs

This study compares the effects of n-channel double-gate FinFETs with fin widths $(W_{\rm fin} ) $ of 10 and 25 nm with those of such devices with back biases and hot carrier injection (HCI. Compared with the device with a wide $W_{\rm fin}$ , the device with a narrow $W_{\rm fin} $ exhibits a larger current tuning range but a more off-state current leakage at a positive back bias because of the forward-biased p-n junction and the higher degradation under HCI. The gate-induced drain leakage significantly deteriorates with a positive back bias after HCI because of the generation of interfacial charges. However, a negative back bias causing hot hole injection during HCI can alleviate the degradation compared with unbiased and positive-biased devices.

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

Abnormal transconductance and transient effects in partially depleted SOI MOSFETs

A transconductance dip, observed in floating body partially depleted SOI devices, is due to transient effects and is reduced with a positive back bias in SOI nMOSFETs. MEDICI simulations show that both hole and electron densities near the front interface fluctuate during the turn-on transient, causing a small decrease and then an increase of the drain current that leads to the transconductance dip. Transient effects also cause an initial current ramp in I DS– V GS characteristics at the start of the gate voltage sweep when the back gate is inverted. The transient effect diminishes as the channel length and channel width decrease and as the back bias increases.