Portable Multimedia Devices Research Articles

LOW POWER DIGITAL FILTERING USING ADAPTIVE APPROXIMATE PROCESSING: FIR FILTER STRUCTURES

Techniques for reducing power consumption in digital circuits have become increasingly important because of the growing demand for portable multimedia devices. Digital filters, being ubiquitous in such devices, are a prime candidate for low power design. Algorithmic approaches to low power frequency-selective digital filtering which are based on the concepts of adaptive approximate processing have been developed and formalized by introducing the class of approximate filtering algorithms in which the order of a digital filter is dynamically varied to provide time-varying stopband attenuation in proportion to the time-varying signal-to-noise ratio (SNR) of the input signal, while maintaining a fixed SNR at the filter output. Since power consumption in digital filter implementations is proportional to the order of the filter, dynamically varying the filter order is a strategy which may be used to conserve power. In this paper we introduce a class of approximate filter structures using FIR digital filter constituent elements. These filter structures are explored and shown to be an important element in the characterization of approximate filtering algorithms.

The Importance of Energy Efficiency in Engineering and Informatics

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

The Importance of Energy Efficiency in Engineering and Informatics

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

FPGA-accelerated adaptive projection-based image registration

In this paper, a high-speed hardware-based image registration is proposed exploiting parallelism and adaptive sampling technique to fulfill the requirement of high-speed portable multimedia devices. This technique computes radial and angular projections in parallel way without converting the image into polar domain, but by adjusting the number of samples along angular direction according to radius length which decreases computational load. Further, a complete image registration algorithm without using any geometric transformation is proposed. The software-based implementation of the proposed algorithm is 1.33 times faster than its latest available method in the literature. The proposed algorithm is mapped in field-programmable gate array (FPGA, Virtex6-xc6vlx760-2-ff1760) and it utilizes $$2.03\%$$ Slice LUTs, $$35.14\%$$ LUT-FF pair and $$1.27\%$$ DSP48E1s; and maximum clock frequency is 266 Mz. The hardware-based implementation of the proposed algorithm is $$10^4$$ times faster than software counterpart.

Asymptotically Optimal Low-Power Digital Filtering Using Adaptive Approximate Processing

Techniques for reducing power consumption in digital circuits have become increasingly important because of the growing demand for portable multimedia devices. Digital filters, being ubiquitous in such devices, are a prime candidate for low-power design. We present a new algorithmic approach to low-power frequency-selective digital filtering which is based on the concepts of adaptive approximate processing. This approach is formalized by introducing the class of approximate filtering algorithms in which the order of a digital filter is dynamically varied to provide time-varying stopband attenuation in proportion to the time-varying signal-to-noise ratio (SNR) of the input signal, while maintaining a fixed SNR at the filter output. Since power consumption in digital filter implementations is proportional to the order of the filter, dynamically varying the filter order is a strategy which may be used to conserve power. From this practical technique we abstract a theoretical problem which involves the determination of an optimal filter order based on observations of the input data and a set of concrete assumptions on the statistics of the input signal. Two solutions to this theoretical problem are presented, and the key results are used to interpret the solution to the practical low-power filtering problem. We construct a framework to explore the statistical properties of approximate filtering algorithms and show that under certain assumptions, the performance of approximate filtering algorithms is asymptotically optimal.

An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic

Nowadays, portable multimedia devices have been widely used in low-power structures. Additionally, using approximate computing and multiple-valued logic (MVL) can lead to lower power consumption. Carbon nanotube field effect transistor (CNTFET), with a determinable threshold voltage, is an appropriate choice for designing MVL circuits. In this study, a new approximate ternary full adder is presented based on CNTFET switching logic with the aim of reducing area and energy consumption. The results obtained by the Synopsys HSPICE simulator with the Stanford 32 nm CNTFET technology show that the average power consumption, delay, and energy consumption of the proposed designs are significantly lower than the other conventional and state-of-the-art CNTFET-based ternary circuits. In addition, the proposed ternary full adder is applied to reduce the steps of a ternary multiplier structure and some important metrics such as normalized error distance and energy-error trade-off are calculated to evaluate the efficiency of the proposed circuits. The layout of the proposed design is also plotted to estimate area consumption. Moreover, the approximate design is used for image processing applications such as image multiplying and image blending and the results are accordingly compared with the exact outputs. Similarly, the evaluated peak signal-to-noise ratio and mean structural similarity index metric indicate that the proposed approximate full adder has a proper accuracy for image processing applications.

FPGA Implementation of Low Power DADDA Multipliers and its Application

Most of the VLSI circuits used adders as a key portion, since they form a base elements of all arithmetic functions. Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithm. We exhibit a new XOR- XNOR component, based on that 4:2 compressor circuit has been designed. The compressor with modified inbuilt logic is proposed for realizations of multipliers. The aim of this paper is to reduce the power consumption of 4:2 compressor without compromising the performance. Power consumption and delay of dadda multiplier using proposed 4:2 compressor have been compared with earlier reported circuits. In digital signal processing application, the FIR filter is designed based on low power proposed approximate dadda multiplier is presented. Simulations are performed using Xilinx ISE 9.2 and microwind tool based on CMOS technology.

Design and Implementation of Booth Multiplier using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. Keyword: Approximate computing, low power, mirror adder. Booths multiplier, Wallace tree multiplier I. INTRODUCTION Digital signal processing (DSP) blocks form the backbone of various multimedia applications used in portable devices. Most of these DSP blocks implement image and video processing algorithms, where the ultimate output is either an image or a video for human consumption. Human beings have limited perceptual abilities when interpreting an image or a video. This allows the outputs of these algorithms to be numerically approximate rather than accurate. This relaxation on numerical exactness provides some freedom to carry out imprecise or approximate computation. We can use this freedom to come up with low-power designs at different levels of design abstraction, namely, logic, architecture, and algorithm. The paradigm of approximate computing is specific to select hardware implementations of DSP blocks. It is shown in (1) that an embedded reduced instruction set computing processor consumes 70% of the energy in supplying data and instructions, and 6% of the energy while performing arithmetic only. Therefore, using approximate arithmetic in such a scenario will not provide much energy benefit when considering the complete processor. Programmable processors are designed for general-purpose applications with no application-specific specialization. Therefore, there may not be many applications that will be able to tolerate errors due to approximate computing. This also makes general-purpose processors not suited for using approximate building blocks. This issue has already been discussed in (13). Therefore, in this paper, we consider application-specific integrated circuit implementations of error-resilient applications like image and video compression.

Towards robust and reliable multimedia analysis through semantic integration of services

Thanks to ubiquitous Web connectivity and portable multimedia devices, it has never been so easy to produce and distribute new multimedia resources such as videos, photos, and audio. This ever-increasing production leads to an information overload for consumers, which calls for efficient multimedia retrieval techniques. Multimedia resources can be efficiently retrieved using their metadata, but the multimedia analysis methods that can automatically generate this metadata are currently not reliable enough for highly diverse multimedia content. A reliable and automatic method for analyzing general multimedia content is needed. We introduce a domain-agnostic framework that annotates multimedia resources using currently available multimedia analysis methods. By using a three-step reasoning cycle, this framework can assess and improve the quality of multimedia analysis results, by consecutively (1) combining analysis results effectively, (2) predicting which results might need improvement, and (3) invoking compatible analysis methods to retrieve new results. By using semantic descriptions for the Web services that wrap the multimedia analysis methods, compatible services can be automatically selected. By using additional semantic reasoning on these semantic descriptions, the different services can be repurposed across different use cases. We evaluated this problem-agnostic framework in the context of video face detection, and showed that it is capable of providing the best analysis results regardless of the input video. The proposed methodology can serve as a basis to build a generic multimedia annotation platform, which returns reliable results for diverse multimedia analysis problems. This allows for better metadata generation, and improves the efficient retrieval of multimedia resources.

2.4Ghz ISM(Industrial Scientific Medical) 밴드에서 간섭을 회피하기 위한 무선 센서 노드의 채널 선택 방법

In recent, ISM (Industrial Scientific Medical) band that is 2.4GHz band authorized free of charge is being widely used for smart phone, notebook computer, printer and portable multimedia devices. Accordingly, studies have been continuously conducted on the possibility of coexistence among nodes using ISM band. In particular, the interference of IEEE 802.11b based Wi-Fi device using overlapping channel during communication among IEEE 802.15.4 based wireless sensor nodes suitable for low-power, low-speed communication using ISM band causes serious network performance deterioration of wireless sensor networks. This paper examined a method of identifying channel status to avoid interference among wireless communication devices using IEEE 802.11b (Wi-Fi) and other ISM bands during communication among IEEE 802.15.4 based wireless sensor network nodes in ISM band. To identify channels occupied by Wi-Fi traffic, various studies are being conducted that use the RSSI (Received Signal Strength Indicator) value of interference signal obtained through ED (Energy Detection) feature that is one of IEEE 802.15.4 transmitter characteristics. This paper examines an algorithm that identifies the possibility of using more accurate channel by mixing utilization of interference signal and RSSI mean value of interference signal by wireless sensor network nodes. In addition, it verifies such algorithm by using OPNET Network verification simulator.

Non-tables look-up search algorithm for efficient H.264/AVC context-based adaptive variable length coding decoding

In general, context-based adaptive variable length coding (CAVLC) decoding in H.264/AVC standard requires frequent access to the unstructured variable length coding tables (VLCTs) and significant memory accesses are consumed. Heavy memory accesses will cause high power consumption and time delays, which are serious problems for applications in portable multimedia devices. We propose a method for high-efficiency CAVLC decoding by using a program instead of all the VLCTs. The decoded codeword from VLCTs can be obtained without any table look-up and memory access. The experimental results show that the proposed algorithm achieves 100% memory access saving and 40% decoding time saving without degrading video quality. Additionally, the proposed algorithm shows a better performance compared with conventional CAVLC decoding, such as table look-up by sequential search, table look-up by binary search, Moon’s method, and Kim’s method.

Implementing Linguistic Landscape investigations with M-learning for Intercultural Competence Development

Portable multimedia devices shape the intensity of intercultural contacts not only through content consumption but also through content creation. Enabling learners to participate in content exchange via the Web 2.0 paradigm (audiences as both media consumers and media creators) can be employed to create new forms of acquiring knowledge. This study demonstrates an application of m-learning in a situated in-the-field examination of cultural diversity with the Linguistic Landscape approach. The application is shown from the pedagogical perspective of authentic, informal learning activities conducted in the framework of connectivism. The examination of cultural diversity is conducted in the context of a local environment, i.e. a location familiar to learners. This paper presents a scenario of m-learning activities intended to demonstrate that cultural awareness is often biased by subjective perspectives and stereotypes. Autonomous discovery of this phenomenon results in elevation of learners' openness toward other cultures, which contributes to intercultural competence development.

Geometric Image Compensation Method for a Portable Projector Based on Prewarping Using 2D Homography

As portable multimedia devices become more popular and smaller, the use of portable projectors is also rapidly increasing. However, when portable projectors are used in mobile environments in which a dedicated planar screen is not available, the problem of geometric distortion of the projected image often arises. In this paper, we present a geometric image compensation method for portable projectors to compensate for geometric distortions of images projected on various types of planar or nonplanar projection surfaces. The proposed method is based on extraction of the two-dimensional (2D) geometric information of a projection area, setting of the compensation area, and prewarping using 2D homography. The experimental results show that the proposed method allows effective compensation for waved and arbitrarily shaped projection areas, as well as tilted and bent surfaces that are often found in the mobile environment. Furthermore, the proposed method is more computationally efficient than conventional image compensation methods that use 3D geometric information.

Optimal complexity scalable H.264/AVC video decoding scheme for portable multimedia devices

Limited computing resources in portable multimedia devices are an obstacle in real-time video decoding of high resolution and/or high quality video contents. Ordinary H.264/AVC video decoders cannot decode video contents that exceed the limits set by their processing resources. However, in many real applications especially on portable devices, a simplified decoding with some acceptable degradation may be desirable instead of just refusing to decode such contents. For this purpose, a complexity-scalable H.264/AVC video decoding scheme is investigated in this paper. First, several simplified methods of decoding tools that have different characteristics are investigated to reduce decoding complexity and consequential degradation of reconstructed video. Then a complexity scalable H.264/AVC decoding scheme is designed by selectively combining effective simplified methods to achieve the minimum degradation. Experimental results with the H.264/AVC main profile bitstream show that its decoding complexity can be scalably controlled, and reduced by up to 44% without subjective quality loss.

Low-Power Digital Signal Processing Using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units and evaluate them to demonstrate the efficacy of our approach. We also derive simple mathematical models for error and power consumption of these approximate adders. Furthermore, we demonstrate the utility of these approximate adders in two digital signal processing architectures (discrete cosine transform and finite impulse response filter) with specific quality constraints. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to existing implementations using accurate adders.

A Memory Efficient No List SPECK (NSK) Wavelet Image Coder for Memory-constrained Applications

In this paper, a fast and memory-efficient listless version of set-partitioned embedded block (SPECK) image coder is proposed. Due to the use of linked lists, the original SPECK algorithm requires large run-time memory, making it unsuitable for memory-constrained applications. The proposed coder replaces linked list with small fixed size static memory, to keep track of blocks in set partitioning only and use only two markers to facilitate coding. Replacement of linked lists with small fixed-size static memory also reduces the memory access time, thereby making it faster than the original SPECK. Simulation results show that the proposed algorithm outperforms SPECK image coder in terms of memory requirement and computational complexity while retaining the coding efficiency and scalability. The proposed coder requires 0.25-bit per pixel state memory which is 3.125% of the memory to store the image. These features make it suitable for resource-constrained portable handheld multimedia devices. Keywords: Image coding, wavelet, SPECK, listless image coder, memory efficient image coder, block

Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC

Variable block-size motion estimation (VBSME) process occupies a major part of computation of an H.264 encoder, which is usually accelerated by bit-parallel hardware architectures with large I/O bit width to meet real-time constrains. However, such kind of architectures increase the area overhead and pin count, and therefore will not be suitable for area-constrained electronic consumer designs such as small portable multimedia devices. This paper addresses this problem by proposing two area efficient least significant bit (LSB) bit-serial architectures with small pin numbers. Both designs take advantage of data reusing technique in different ways for sum of absolute differences (SAD) computation and reading reference pixels, leading to a considerable reduction of memory bandwidth. The first architecture propagates the partial SAD and sum results and broadcasts the reference pixel rows whereas the second design reuse the SAD of small blocks and has a reconfigurable reference buffer leading to a better memory bandwidth when using hardware parallelism. The proposed designs benefit from several optimization techniques including an efficient serial absolute difference architecture, word length reduction by parallelism, bit truncation, mode filtering, and macroblock (MB) level subsampling, which significantly enhance their performances in terms of silicon area, throughput, latency, and power consumption. The first and second designs can support full search VBSME of 720?×?480 video with 30 frames per second (fps), two reference frames, and [?16, 15] search range at a clock frequency of 414 MHz with 29.28 k and 31.5 k gates, respectively.

Micro audio directional system for portable multimedia devices

A micro audio directional system for portable multimedia devices is investigated as a novel loudspeaker which can provide privacy listening service. It can generates audible sound with high directivity in a narrow conical beam by an ultrasonic transducer array. A piezoelectric micromachined ultrasonic transducers (pMUT) array and a PZT ceramic wafer transducers array are presented respectively. The testing results of impedance, frequency response and sound pressure level characteristics are described and compared. A prototype with PZT ceramic wafer transducers array is constructed for mobile phone usage and its acoustic characteristics are measured. The experiment results indicate the feasibility of utilising the audio directional system with low power consumption and micro size in portable multimedia devices as well as in mobile phone.

Pooling-Based Intra Prediction Mode Coding for Mobile Video Applications

The demand of real-time yet high quality video encoding for portable multimedia devices is increasingly strong. The state of the art H.264/AVC standard provides much higher coding efficiency than its predecessors. However, its high computational complexity of encoding is not suitable for battery-powered mobile devices. In this paper, we introduce a low complexity video encoding scheme based on new pooled macroblock modes mainly targeted for battery-operated portable devices. Since the motion prediction and intra prediction take most of the computation and thus battery consumption, restriction of prediction block sizes is essential in implementing a low complexity encoder. However, if this is not done carefully, it may result in unacceptable degradation of coding efficiency. The problem is overcome by developing new macroblock coding modes which are computationally trivial but effective in coding efficiency. Experimental results with several well-known video test sequences verify a far better performance of the proposed method against the standard H.264/AVC encoder operated in low-complexity configuration. Also we evaluate how less power consumption the proposed low complexity encoder actually consumes compared to that of the H.264/AVC baseline profile.

Phase-shift self-oscillating class-D audio amplifier with multiple-pole feedback filter

A self-oscillating class-D audio amplifier employing a multiple-pole feedback filter is introduced intended for portable multimedia devices. As the oscillation is based on the Barkhausen's criterion, the signal-dependent oscillation frequency is of great concern. Employing higher-order filters contributes to the stable oscillation frequency depending on the input amplitude as well as improves PSRR and THD. The concept is revealed comparatively with other works, and a design implemented in a 0.35um CMOS process under 3.3V supply is proposed and verified.