Porous Ultra Low-k Dielectrics Research Articles

Impact of organic linking and terminal groups on the mechanical properties of self-assembly based low-k dielectrics

The impact of terminal and linking organic groups on the mechanical stability of self-assembly based porous ultralow-k dielectrics was investigated by nanoindentation and four-point bending tests in conjunction with quantitative FTIR analysis. Using a set of six porous low-k dielectric films functionalized with alkyl- and aryl-based groups, we demonstrated that both elastic and fracture properties can be sensitive to the type of embedded linking or terminal groups. Based on the obtained correlations between the material composition and the mechanical properties, two approaches for improvement of fracture toughness in low-k dielectrics are proposed.

Surface-Localized Sealing of Porous Ultralow-k Dielectric Films with Ultrathin (

Semiconductor integrated circuit chip industries have been striving to introduce porous ultralow-k (ULK) dielectrics into the multilevel interconnection process in order to improve their chip operation speed by reducing capacitance along the signal path. To date, however, highly porous ULK dielectrics (porosity >40%, dielectric constant (k) <2.4) have not been successfully adopted in real devices because the porous nature causes many serious problems, including noncontinuous barrier deposition, penetration of the barrier metal, and reliability issues. Here, a method that allows porous ULK dielectrics to be successfully used with a multilevel interconnection scheme is presented. The surface of the porous ULK dielectric film (k = 2.0, porosity ∼47%) could be completely sealed by a thin (<2 nm) polymer deposited by a multistep initiated chemical vapor deposition (iCVD) process. Using the iCVD process, a thin pore-sealing layer was localized only to the surface of the porous ULK dielectric film, which could minimize the increase of k; the final effective k was less than 2.2, and the penetration of metal barrier precursors into the dielectric film was completely blocked. The pore-sealed ULK dielectric film also exhibited excellent long-term reliability comparable to a dense low-k dielectric film.

Mechanical Stability of Porous Low-k Dielectrics

This paper reviews the mechanical and fracture properties of porous ultralow-k dielectrics with the focus on chip package interaction related issues. It is shown that the mechanical and fracture properties of porous ultralow-k dielectric films are closely linked with porosity, pore morphology, network structure and deposition technology, while their fracture properties are also sensitive to reactive species in the environment. The survivability of low-k dielectrics upon integration, package assembly and subsequent reliability tests is therefore a combination of their mechanical stability, fracture properties, the specific mechanical or thermo-mechanical load and environmental effects.

웨이퍼 레벨 3D Integration을 위한 Ti/Cu CMP 공정 연구

Cu 본딩을 이용한 웨이퍼 레벨 적층 기술은 고밀도 DRAM 이나 고성능 Logic 소자 적층 또는 이종소자 적층의 핵심 기술로 매우 중요시 되고 있다. Cu 본딩 공정을 최적화하기 위해서는 Cu chemical mechanical polishing(CMP)공정 개발이 필수적이며, 본딩층 평탄화를 위한 중요한 핵심 기술이라 하겠다. 특히 Logic 소자 응용에서는 ultra low-k 유전체와 호환성이 좋은 Ti barrier를 선호하는데, Ti barrier는 전기화학적으로 Cu CMP 슬러리에 영향을 받는 경우가 많다. 본 연구에서는 웨이퍼 레벨 Cu 본딩 기술을 위한 Ti/Cu 배선 구조의 Cu CMP 공정 기술을 연구하였다. 다마싱(damascene) 공정으로 Cu CMP 웨이퍼 시편을 제작하였고, 두 종류의 슬러리를 비교 분석 하였다. Cu 연마율(removal rate)과 슬러리에 대한 <TEX>$SiO_2$</TEX>와 Ti barrier의 선택비(selectivity)를 측정하였으며, 라인 폭과 금속 패턴 밀도에 대한 Cu dishing과 oxide erosion을 평가하였다. The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to <TEX>$SiO_2$</TEX> and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

Pore Sealing of Porous Ultralow-k Dielectrics by Self-Assembled Monolayers Combined with Atomic Layer Deposition

Due to its excellent step coverage characteristics, atomic layer depositions (ALD) deposit their material not only on top of underlying surfaces but also into the pores of porous low-k films. In this study, the film characteristics caused by pre-treatments of the low-k material, followed by deposition of self assembled monolayers (SAMs) from an 11-cyanoundecyltrichlorosilane precursor and finally by an HfO2 Atomic Layer Deposition were determined. By adequate optimization of the surface treatment, the SAM deposition and the ALD it was possible to obtain complete pore sealing after ALD, without penetration of the Hf into de porous low-k film.

Effect of TaN Stoichiometry on Barrier Oxidation and Defect Density in 32nm Cu/Ultra-Low K Interconnects

AbstractThe scaling of BEOL interconnect technology in ULSI circuitry requires the integration of Cu wiring with ultra-low K (ULK) dielectrics. We present the results of a study of the interaction between different-stoichiometry Ta(N)/Cu barrier processes and porous ULK dielectrics (k=2.4) at 32nm groundrules Auger and diffraction analysis of blanket wafers was used to benchmark two different stoichiometries of TaN barrier deposited using commercially-available ionized PVD sources. Comparison TEM and EDX/EELS images indicates that barrier oxidation is occurring in the low nitrogen-content Ta(N) barrier, which is absent at the higher stoichiometry. These differences are further manifested in defect-density analysis of patterned wafers comparing the two processes. These results illustrate the critical importance the TaN barrier properties play in enabling the integration of Cu/ULK interconnects at 32nm at beyond.

A self-similarity model for dielectric constant of porous ultra low-k dielectrics

A self-similarity model applying the Sierpinski carpet approximation for the effective dielectric constant of nanoporous low-k dielectrics is proposed based on the statistically self-similar characteristics of pore size distributions in the medium and on the ‘mixture rule’ technique. The proposed model for the dielectric constant is expressed as a function of porosity (related to stage n of Sierpinski carpet) and the dielectric coefficient of components of the medium. The model predictions are compared with the existing experimental data and with other model predictions, and good agreement is obtained between the present model predictions and the experimental data. The proposed technique may have the potential of analysing other properties such as thermal conductivity and Young's modulus.