Polysilicon Thin Film Transistors Research Articles

The Fabrication and Characterization of Direct Conversion Flat Panel X-ray Imager with TlBr Film

The novel direct conversion flat panel detectors (FPDs) utilizing thallium bromide (TlBr) films are developed and characterized in this study. Thin TlBr films, deposited using an evaporation technique, achieved thicknesses of 10 μm and 50 μm. A pixel sensor array, with a pixel size of 235 × 235 μm2 and a sensitive area of 29.61 × 39.48 mm2, was developed using low-temperature polysilicon thin-film transistor (LTPS TFT) technology as the initial study to explore performance characteristics of developed imaging system. The TlBr film was characterized based on the current-voltage (I-V) profile, showing a resistivity of 2.78 × 101⁰ Ω·cm. The LTPS TFT showed a leakage current of about 10-13 A, while the noise of TlBr FPD system was around 104 e- rms, primarily limited by the readout system. The detector system was characterized using radiation from an X-ray tube with a voltage in the range of 30 kV to 100 kV and a current of 2 mA, involving an X-ray test chart as the object with the processing time of 18.15 to 18.30 ms per frame. Based on the contrast and contrast-to-noise ratio (CNR) values, the 10 μm and 50 μm TlBr FPD clearly captured the image in operation between 30 kV and 100 kV. The 50 μm TlBr FPD demonstrated improved sensitivity, showing pixel values with 10 times higher intensity and enhanced line pair detail at 30 kV X-ray operation. The 10 μm TlBr achieved spatial resolution of 267 μm full width at half maximum (FWHM), while the 50 μm TlBr achieved 250 μm FWHM. In the X-ray imaging demonstration, the shape and structure of anchovy was clearly distinguished. The TlBr film FPD presents promising potential for a room temperature X-ray imager.

A 6T1C pixel circuit compensating for TFT electrical characteristics variations, voltage drop, and OLED degradation

A voltage-programmed pixel circuit based on low-temperature poly-silicon (LTPS) thin-film transistors (TFTs) is presented for active-matrix organic light-emitting diode (AMOLED) displays. The circuit consists of six p-type transistors and one capacitor (6T1C). During the extraction stage, the circuit extracts the driving TFT’s threshold voltage and the power supply voltage. During the data input stage, the circuit generates a charging voltage, which is associated with the driving TFT’s mobility and the OLED’s threshold voltage. Consequently, the pixel circuit, using only one capacitor, compensates not only for the TFT’s electrical characteristics variations, i.e., the threshold voltage variation and mobility variation, but also for the power supply voltage drop and the OLED degradation. The circuit simulation results reveal that the OLED current error rates (CERs) are lower than 5.09% when the threshold voltage varies by ±0.5V, lower than 3.61% when the mobility varies by ±30%, and lower than 9.16% when the voltage drop varies by −0.5V in the data voltage range.

A study of bottom-contact organic thin-film transistors based on source/drain tunneling structure

During recent years, OLED display has become one of the important products for consuming electronics and industrial domains. For AMOLED display, thin film transistor (TFT) is necessary for driving OLED devices. As the polysilicon and amorphous silicon TFTs have become mainstreams, organic thin film transistors (OTFTs) have also been proposed and shown their advantages in low-temperature process compatible with flexible substrates. However, OTFTs applicable to drive OLED generally adopt bottom-contact configuration. The performance of bottom-contact OTFTs are often inferior relative to top-contact OTFTs, due primarily to the high contact resistance of bottom-contact OTFTs. To overcome this disadvantage, the source/drain tunneling structure is proposed in this article. This tunneling structure can not only decorate the electrode/organic semiconductor interface to obtain a good metal-semiconductor contact, but also can form a MOS configuration at source/drain contact, so as to increase the carrier concentration at the contact to further reduce contact resistance. In this paper, a typical P-type high-mobility small molecule material of Pentacene is employed as the active layer of the OTFT, while CuO film, Polystyrene (PS) film is separately selected as the tunneling layer at source/drain contact. The diverse parameters, especially field effect mobility, were analyzed by analyzing electrical characteristics of the top-contact and bottom-contact OTFTs. In addition, the contact resistances were confirmed by line transfer method. The bottom-contact OTFTs incorporating tunneling layer own a maximum hole mobility of 0.143cm2/V·s.This suggested that the source/drain tunneling structure can indeed improve the electrical characteristics of bottom-contact OTFT, and further improvement is necessitated to achieve the high performance comparable to top-contact device.

38.2: An Accurate and Stable PWM Pixel Circuit Based on LTPO TFTs for AM‐Micro‐LED Display

A pulse-width-modulation (PWM) pixel circuit for Micro-LED displays is proposed based on low-temperature poly-silicon and oxide (LTPO) thin-film transistors (TFTs). The pixel circuit features fast PWM transition, as the PWM falling-time is less than 20 μs thanks to the high-gain dynamic inverter. Furthermore, the proposed pixel circuit can compensate the degradation and non- uniformities of TFT characteristics of LTPO TFTs through auto- zeroing configuration of the dynamic inverter and a diode- connected threshold voltage compensation structure. The error rate of luminous time is less than 3.2% and the error rate of current is less than 1% under VTH shift of oxide TFT ±2 V or LTPS TFT ±1 V.

Gate Driver on Array With Multiple Outputs and Variable Pulse Widths for Low-Temperature Polysilicon and Oxide (LTPO) TFTs Driven AMOLED Displays

A gate driver on array (GOA) circuit was proposed for low-temperature polysilicon and oxide (LTPO) thin-film transistor (TFT) hybrid-driven active matrix organic light-emitting diode (AMOLED) displays with both high and low refresh rate operation. The GOA generates multiple types of scanning signals by reusing shift registers so that three signal pulses are output parallelly within a single stage to scan p- and n-type switching TFTs and emission TFT of the AMOLED pixels, respectively, leading to a 30% reduction in the layout area. Furthermore, the pulse-width of the scan signals for the emission TFT can be programed simply by changing the number of input pulses to vary refresh rates. The fabricated GOAs work well even with the pulse width reduced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.9 \mathbf {\mu }\text{s}$ </tex-math></inline-formula> .

Effects of Static and Repetitive Uniaxial Bending Strains on the Electrical Properties and Trap Characteristics of Flexible Low-Temperature Polysilicon Thin-Film Transistors

Changes in the electrical properties and trap characteristics of flexible low-temperature polysilicon thin-film transistors (TFTs) under the application of uniaxial bending strains and during repetitive bending cycles were investigated. When the bending strain increased, the transfer curve showed a negative shift, the output current decreased, and the subthreshold slope increased. After the bending strains were removed, the electrical performance showed recovery behavior, but the device performance could not return fully to its original state. The devices were also subjected to repetitive bending cycles. The transfer curves showed a positive shift after <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$ </tex-math></inline-formula> bending cycles and the output current increased. Using the transient current method, it was established that the detrapping time constant of the traps decreased and the peak amplitudes increased as a result of both the bending strain and the bending cycles. However, while the trap activation energy was not changed by static bending, it did decrease after the repetitive bending cycles. Both the changes in the electrical properties and the time constant spectra confirm that the trap state density increased as a result of the bending processes. However, the different trapping behaviors contributed to different degradations in the device’s electrical properties.

Highly Robust Flexible Poly-Si Thin Film Transistor Under Mechanical Strain With Split Active Layer for Foldable Active Matrix Organic Light Emitting Diode Display

We report a novel active split structure of low-temperature polysilicon (LTPS) thin film transistor (TFT) on polyimide (PI) substrate showing robust electrical performance under mechanical strain. The compressive and tensile bending tests were carried out with cylinders of radii 3, 2 and 1 mm respectively. The active split TFT exhibits much more stable electrical performance than the conventional TFT. The conventional LTPS TFT shows electrical failure due to the crack generation during tensile or compressive bending test carried out with 1 mm radius cylinder. The split poly-Si islands could resist crack formation/propagation, resulting in a robust electrical performance.

High mobility achieved in InGaZnO TFT with vacuum-gap as insulating layer

In this Letter, an amorphous In-Ga-Zn-O (InGaZnO) thin-film transistor (TFT) structure with a vacuum-gap as a dielectric layer is proposed and investigated. Field-effect conduction at the vacuum/InGaZnO interfaces exhibits extraordinary effective mobility (μ) up to 65 ± 20 cm2 V−1 s−1, while the μ is only around 10 cm2 V−1 s−1 at the SiO2/InGaZnO interfaces with similar film processing conditions. Temperature-dependent transport is performed for deeper insight of the physical origin of the much higher μ at the vacuum/InGaZnO interface. We have found the density of states (DOS) of tail states is notably lower for the transport near the vacuum (8 × 1017 compared to 1.1 × 1019 cm−3 eV−1 at the SiO2/vacuum interface). These indicate that traditional dielectric materials like SiO2 have strong effects on the charge transport degradation in InGaZnO TFTs by introducing extra energetic disorders, and the intrinsic charge transport in InGaZnO is potentially approaching those in poly-silicon TFTs. Exploring a high-quality dielectric layer should be one effective way to further optimize the electrical performance in TFTs based on amorphous oxide semiconductors.

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

We report detailed fabrication and characterization of poly-Si thin-film transistors (TFTs) with T-shaped gate (T-gate) and lightly-doped drain (LDD) structures. The formation of the LDD underneath the wings of a T-gate primarily relies on the shadowing of implanted dopants during the implantation of source and drain. Therefore, the fabrication of LDD structures in our proposed T-gate poly-Si TFTs can save a number of process steps as compared to conventional poly-Si TFTs with LDD structures. Our fabricated T-gated poly-Si TFTs with LDD structures not only exhibit suppressed off-state leakage current but also show a significant improvement in on-state current as compared to that of conventional poly-Si TFTs with the same top-gate dimension.

A mirrored 5T1C OLED pixel circuit for compensating characteristics variations and voltage drop

A pixel circuit with p-type low temperature poly-silicon thin-film transistors (TFTs) is presented for active-matrix organic light-emitting diode displays. This circuit consists of five TFTs and one capacitor. In the circuit, the characteristics, i.e., the threshold voltage and the mobility, are extracted by the mirroring structure, and an adaptive voltage is generated at the gate of the TFT in the programming stage. Therefore, only one capacitor is needed to compensate both the threshold voltage variation and the mobility variation. Meanwhile, in the circuit, the voltage drop of the power line is also compensated. Moreover, the circuit can prevent the image flicker because the organic lighting-emitting diode (OLED) only operates in the emission stage. The circuit simulation results indicate that the OLED current error rates are lower than 4.61% when the threshold voltage variation is ±0.5V, lower than 6.92% when the mobility variation is ±30%, and lower than 3.96% when the voltage drop is −0.5V.

P‐15.4: A newly Integrated Ambient Light sensor with full in‐cell structure

In this paper, we present a novel integrated light‐dependent sensor which can be used to detect the illuminance of the ambient light. Based on the low temperature polysilicon (LTPS) thin film transistor (TFT) process and photosensitivity of a‐Si, the sensor can realize 0‐10K lux of the monitor range and 0.5 lux/step. It saves more space for terminal devices which will also facilitates the full screen display.

Effect of Biaxial Bending Strains on the Electrical Characteristics of Flexible Low-Temperature Polysilicon Thin-Film Transistors

The change of electrical properties of flexible low-temperature polysilicon (LTPS) thin-film transistors (TFTs) under biaxial bending strains was studied. Biaxial strains were applied using a ring-on-ring bending test rig. The magnitude of the strain was determined by theoretical calculations and finite-element simulations. With an increase in strain, the transfer curve shifted to a negative bias. At a biaxial strain level of 12%, the threshold voltage decreased by 27%, the field-effect mobility decreased by 13%, and the subthreshold slope increased by 25%. It had a more significant effect on the property changes than the uniaxial strain; this difference may be attributed to additional trap states generated by the biaxial strain. The analysis showed that the trap density increased when the strain level increased. The contributions of the increases in the grain-boundary trap state density and the interface trap state density to the degradation in the electrical properties were derived to be 10% and 90%, respectively. After removal of the biaxial bending strains, the electrical performance showed recovery behavior, but the performance could not return fully to its original state.

Simplified EKV model parameter extraction in polysilicon MOSFETs

We present an easy but effective method to extract the four parameters of the simplified Enz–Krummenacher–Vittoz (sEKV) MOSFET model. The procedure, which is based on direct lateral optimization, is tested using measurements from experimental polycrystalline silicon Thin Film Transistors (TFTs) of various channel lengths and widths. We demonstrate that this basic MOSFET model is able to reasonably describe the saturation transfer characteristics of these polysilicon TFTs. Furthermore, we evaluate the computational adeptness for extracting the four sEKV parameters of the lateral optimization fitting procedure as compared to the more traditional vertical optimization one.

Strain distribution and electrical characteristics of flexible low-temperature polysilicon thin film transistors under biaxial bending

This paper investigates the strain distribution of flexible p-channel low temperature polycrystalline silicon thin film transistors under biaxial bending. The strain distribution of LTPS TFTs under different bending conditions is analysed by finite element analysis. \U0001d6c6r and \U0001d6c6θ are essentially equal and constant within the load ring. The finite element analysis shows that when the biaxial bending strain condition is 2.5%, the strain distribution is mainly concentrated at the contact angle between the electrode and the oxide layer. This strain is significantly greater than the overall strain of the device, which is the main reason for the bending performance of the device. We found that under biaxial bending, the threshold voltage shifts towards the negative axis as the biaxial strain increases. Within this strain range, these electrical properties are evident under biaxial strain conditions. Comparing theoretical threshold voltage shifts based on energy band changes with experimental results under biaxial strain, it was found that changes in trap density should also contribute to the threshold voltage shift.

Strategies for Applications of Oxide-Based Thin Film Transistors

Due to the untiring efforts of scientists and researchers on oxide semiconductor materials, processes, and devices, the applications for oxide-based thin film transistors (TFTs) have been researched and promoted on a large scale. With the advantages of relatively high carrier mobility, low off-current, good process compatibility, optical transparency, low cost, and especially flexibility, oxide-based TFTs have already been adapted for not only displays (e.g., liquid crystal display (LCD), organic light emitting diode (OLED), micro-light-emitting diode (Micro-LED), virtual reality/augmented reality (VR/AR) and electronic paper displays (EPD)) but also large-area electronics, analog circuits, and digital circuits. Furthermore, as the requirement of TFT technology increases, low temperature poly-silicon and oxide (LTPO) TFTs, which combine p-type LTPS and n-type oxide TFT on the same substrate, have drawn further interest for realizing the hybrid complementary metal oxide semiconductor (CMOS) circuit. This invited review provides the current progress on applications of oxide-based TFTs. Typical device configurations of TFTs are first described. Then, the strategies to apply oxide-based TFTs for improving the display quality with different compensation technologies and obtaining higher performance integrated circuits are highlighted. Finally, an outlook for the future development of oxide-based TFTs is given.

Analysis of self-heating-related instability in n-channel low-temperature polysilicon TFTs with different S/D contact hole densities

This study examines self-heating-related instability in n-channel low-temperature polysilicon thin-film transistors with different source/drain contact hole densities. Devices with more contact holes exhibit a higher on-current without additional parasitic capacitance, further enhancing the RC delay property. For high-current-induced self-heating stress, a device with one contact hole has one hump due to the kink effect. However, a device with six contact holes has two humps, induced by the kink effect and thermionic field emission. COMSOL simulations of heat distribution and energy bands are performed to examine the different degradation behaviors, and then physical models are proposed.

Large‐area, high‐temperature stainless steel foil substrate for manufacturing low‐cost and flexible CMOS polysilicon TFTs

AbstractA large‐area stainless steel foil substrate which is compatible with high‐temperature (&gt;800°C) processing was developed to support a hybrid printed and conventional process technology to fabricate polysilicon thin‐film transistors (TFTs). The purpose was to build a platform that could lead to low‐cost, roll‐to‐roll manufacturing of polysilicon TFTs. To fabricate a self‐aligned top‐gate TFT structure, a screen‐printed dopant process, which requires high‐temperature activation, was developed to substitute capital‐intensive ion implantation. For the pilot line process, a 300‐mm2 and 100‐μm‐thick stainless steel substrate made of an alloy with a low thermal expansion coefficient (CTE) was chosen. Then, the foil finishing process was optimized to achieve flatness and minimize surface roughness. A barrier and dielectric encapsulation were developed to prevent trace metal diffusion from the substrate into the active layers. The polysilicon TFTs were then evaluated with static and dynamic bending tests.

Study of traps in low-temperature polysilicon thin film transistors using a current transient method

The trap characteristics of low-temperature polysilicon thin film transistors (TFTs) are studied using a current transient method that is based on the trapping and detrapping of charge carriers from the trap sites in the device. Analysis of the measured current transient curve allowed three types of detrapping behavior to be identified, each of which displayed a different time constant, activation energy, and spatial position. This current transient method can be integrated into the negative bias temperature instability stress test used for the reliability study. The peak amplitudes of the traps increase because of the stress applied in the test, thus demonstrating that the degradation mechanism of the TFTs is closely related to changes in the traps in these devices.

Slot-die coating of silicon ink for volume production of CMOS polysilicon TFTs

A large-area polysilicon film was formed from slot-die coating of cyclopentasilane based silicon ink and laser crystallization. In this article a study of silicon ink preparation and selection, slot-die coater setup, coating and laser crystallization is described. The polysilicon film was applied to fabricate complementary metal oxide semiconductor (CMOS) thin film transistors (TFTs) which were used to develop and demonstrate near field communication devices. This was part of a hybrid process flow consisting of conventional lithography and printing to fabricate CMOS TFTs. Slot-die coating of silicon ink on a 300 mm square 100 μm thick stainless steel substrate is a key building block of this hybrid process flow to subtract and replace high capital cost plasma enhanced chemical vapor deposition (PECVD), ion implantation and silicon wafers. With slot-die coating of silicon ink, a silicon layer formation equivalent to PECVD in quality was achieved.

Stacked-Interconnect for Monolithic Integration of Low-Temperature Polysilicon and Amorphous Metal-Oxide Thin-Film Transistors

While offering a range of practical benefits, the monolithic integration of low-temperature polysilicon (LTPS) and amorphous metal-oxide thin-film transistors presents several incompatibility issues regarding materials and processes. Presently addressed are two critical ones arising from the back-end processes of contact treatment and metallization. Both are resolved by employing a stacked-interconnect consisting of two conductor layers, with each layer forming the preferred contact electrodes for one of the two types of transistors. At the expense of a slight increase in process complexity, a narrow distribution of low specific contact resistance ( ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> Ω·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) for both types of transistors was obtained, thus giving rise to more consistent transistor characteristics. Inverters consisting of complementary top-gate LTPS pull-up and bottom-gate indium-gallium-zinc oxide pull-down transistors were demonstrated, exhibiting a gain of 40 V/V and a rail-to-rail full swing.