Polysilicon Gate Depletion Effect Research Articles

Reduction of Polysilicon Gate Depletion Effect in NMOS Devices Using Laser Thermal Processing

One critical issue in advanced semiconductor processing is to have adequate dopant activation in the polycrystalline silicon (poly-Si) gate to minimize carrier depletion at the gate/gate oxide interface (poly-depletion). We demonstrate a novel technique, using laser thermal processing, to form super-doped n + -poly-Si gates on ultrathin gate oxides. The results indicate that the poly-depletion effect in n-channel metal-oxide-semiconductor (NMOS) devices can be significantly reduced if the entire as-deposited amorphous silicon gate melts upon laser irradiation. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after laser processing at a high fluence.

Impact of poly-gate depletion on MOS RF linearity

The distortion behavior for thin oxide MOS transistors can be degraded due to polysilicon-gate depletion effects. The nonlinear, bias-dependent gate capacitance for thin oxide MOSFET's results in significant 2nd-order derivatives in gate capacitance, (/spl part//sup 2/C(V/sub gs/)//spl part/V/sub gs//sup 2/), which in turn results in substantial 3rd-order derivative contributions to drain current, (/spl part//sup 3/I/sub ds///spl part/V/sub gs//sup 3/). This may restrict the use of very-thin oxide MOSFET's in RF applications.

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.

Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-/spl kappa/ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization.

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs

Ion implantation, followed by annealing process, often leads to nonuniform doping and considerable depletion effect in the polysilicon gate of submicron MOS devices. Such an effect can alter notably the subthreshold characteristics and invalidate the conventional subthreshold current model. This paper studies the polysilicon-gate depletion effects on the subthreshold behavior based on results obtained from two-dimensional device simulation. An empirical expression is also suggested to describe the subthreshold current including the depletion effect.

Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

The electrical characteristics (C-V and I-V) of n+ - and p+ -polysilicon-gated ultrathinoxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15-20 A. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface.

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

Experimental studies on deep submicron CMOS scaling

N- and surface channel p-MOSFETs and CMOS ring oscillators with channel lengths down to and physical gate oxide thicknesses of 2.5 nm-5.8 nm were fabricated. The parasitic SD series resistance, threshold voltages, finite thickness of inversion layer including quantum and polysilicon gate depletion effects, drain saturation current, load capacitance of ring oscillator and ring oscillator speed were characterized at voltages from 1.5 to 3.3 V. The results confirmed the accuracy of the analytical models recently developed. The existence of an optimum gate oxide for given , , and is demonstrated from both the analytical model and the experimental data.

Separation of d.c. and a.c. competing effect of polysilicon-gate depletion in deep submicron CMOS circuit performance

This paper reports competing behavior between the d.c. and a.c. polysilicon-gate depletion effect (PDE) on deep-submicron CMOS circuit perfomance. The d.c. and a.c. PDE components are separated quantitatively and their competing effect demonstrated. Their dependence on polysilicon doping concentration and oxide thickness are examined. The study indicates that the d.c. PDE is more dominant than the a.c. PDE in circuit performance and this dominance can be lessened when transistors have a thinner gate oxide.