Polysilicon Diodes Research Articles

Gate Driver on Array With Multiple Outputs and Variable Pulse Widths for Low-Temperature Polysilicon and Oxide (LTPO) TFTs Driven AMOLED Displays

A gate driver on array (GOA) circuit was proposed for low-temperature polysilicon and oxide (LTPO) thin-film transistor (TFT) hybrid-driven active matrix organic light-emitting diode (AMOLED) displays with both high and low refresh rate operation. The GOA generates multiple types of scanning signals by reusing shift registers so that three signal pulses are output parallelly within a single stage to scan p- and n-type switching TFTs and emission TFT of the AMOLED pixels, respectively, leading to a 30% reduction in the layout area. Furthermore, the pulse-width of the scan signals for the emission TFT can be programed simply by changing the number of input pulses to vary refresh rates. The fabricated GOAs work well even with the pulse width reduced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.9 \mathbf {\mu }\text{s}$ </tex-math></inline-formula> .

Polysilicon devices as a highly compatible ESD protection with modulable voltage and low capacitance

The electronic circuits fabricated in a variety of technologies for different applications are all vulnerable to the electrostatic discharge (ESD) event. In this paper, polysilicon devices are investigated as ESD protection because of the noticeable advantages such as compatibility with several technologies, low parasitical capacitance, and little noise coupling. By forming the p-i-n diode in the polysilicon layer and stacking them together, the single polysilicon diode (SPD) and cascaded polysilicon diode (CasPD) are implemented in the 0.35 [Formula: see text] high voltage diffusion process. Through DC IV/CV, transmission line pulse (TLP), and zipping test, the CasPD presents as ESD protection for an S-band RF power amplifier, with high process-compatibility, modulable voltage, low leakage current and parasitic capacitance.

A Novel Low Turn-Off Loss and Snapback-Free Reverse-Conducting SOI-LIGBT With Integrated Polysilicon Diodes

A novel reverse-conducting (RC) lateral insulated gate bipolar transistor based on the silicon-on-insulator (SOI-LIGBT) with integrated parallel/antiparallel polysilicon diodes ( $\text{D}_{F}$ and $\text{D}_{R}$ ) on the top of the anode active region is proposed and investigated by simulation. During the turn-off transient, the major part of the excess electron current flows through the parallel diode $\text{D}_{F}$ which achieves a low turn-off loss ( $E_{ \mathrm{\scriptscriptstyle OFF}}$ ). While during the forward-conducting state, the voltage across the p+-anode/n-buffer junction can rapidly increase to the junction’s built-in potential ( ${V}_{\text {bi}}$ ) at low anode current, which results in snapback immunity. Moreover, the antiparallel diode $\text{D}_{R}$ enables the proposed device to realize RC capability. Simulation results reveal that the proposed RC-LIGBT can realize superior $E_{ \mathrm{\scriptscriptstyle OFF}}$ - $V_{ \mathrm{\scriptscriptstyle ON}}$ tradeoff relationship than both the conventional LIGBT and the separated shorted-anode LIGBT (SSA-LIGBT). When $E_{ \mathrm{\scriptscriptstyle OFF}}$ is 0.44 mJ/cm2, $V_{ \mathrm{\scriptscriptstyle ON}}$ of the proposed RC-LIGBT is 1.95 V, which is 0.47 V lower than that of the SSA-LIGBT. Under ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 1.95 V, $E_{ \mathrm{\scriptscriptstyle OFF}}$ of the proposed RC-LIGBT is 0.44 mJ/cm2, which is reduced by 44.3% than that of the conventional LIGBT. Furthermore, the reverse recovery charge ( ${Q}_{\text {rr}}$ ) of the proposed device is reduced by 25.8% compared with that of the conventional one. In addition, diodes $\text{D}_{F}$ and $\text{D}_{R}$ and the thin oxide layer below can be fabricated during the implementation of the polysilicon gate. Therefore, there is no extra difficulty in the fabrication process of the proposed RC-LIGBT.

Development of polysilicon devices for microfluidic thermal instrumentation

In microfluidics applications such as biology and chemistry, for which lab-on-chip and microreactors have been developed, the temperature control through a microchannel is of first interest. In this paper, we present a simple and generic technology for thermal sensing applications based on the fabrication of polysilicon diodes that can be implemented either on silicon, fused silica or silicon carbide substrates. Thermal sensitivities were characterized and as a first experimental approach a dedicated set-up was developed for the temperature measurement of a water flow through a SU-8 microchannel.

A Compact CMOS Compatible Oxide Antifuse With Polysilicon Diode Driver

A very compact one-time-programmable memory consisting of an oxide antifuse and a polysilicon diode driver is proposed in this brief. The memory cell is constructed using a standard CMOS process without any additional masks to reduce the fabrication cost. The design method to achieve the required performance of various components is presented in detail. The technology has been demonstrated with a fabricated chip from a standard 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> CMOS TSMC technology.

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.

Low-leakage diode-triggered silicon controlled rectifier for electrostatic discharge protection in 0.18-μm CMOS process

A diode-triggered silicon controlled rectifier (DTSCR) is being developed as an electrostatic discharge (ESD) protection device for low voltage applications. However, DTSCR leaks high current during normal operation due to the Darlington effect of the triggering-assist diode string. In this study, two types of diode string triggered SCRs are designed for low leakage consideration; the modified diode string and composite polysilicon diode string triggered SCRs (MDTSCR & PDTSCR). Compared with the conventional DTSCR (CDTSCR), the MDTSCR has a much lower substrate leakage current with a relatively large silicon cost, and the PDTSCR has a much lower substrate leakage current with similar area and shows good leakage performance at a high temperature. Other DTSCR ESD properties are also investigated, especially regarding their layout, triggering voltage and failure current.

Experimental study and two-dimensional modeling of avalanche breakdown voltage in polycrystalline silicon p-n junctions

A two-dimensional (2D) model of the avalanche breakdown mechanism is examined to achieve a lateral polycrystalline silicon (polysilicon) p+-n diode with high forward current and high breakdown voltage (BV). Samples with different film thicknesses (tf) were deposited by low-pressure chemical vapor deposition process. The p+ zone and n zone are doped by ionic implantation with boron and phosphorus, respectively. The measured current-voltage (I-V) characteristics show that BV varies between 6.4, 7.5, and 8.25V when tf varies between 250, 350, and 450nm, respectively. These data also show that when tf decreases, the forward current is high, the leakage current becomes higher under reverse bias, and BV decreases. We reveal that the breakdown phenomenon of our samples is dominated by the impact ionization effect. A 2D simulation of avalanche breakdown voltage versus the critical parameters of polysilicon diodes is implemented. The algorithm is based on the solution of Poisson’s equation and calculating the ionization integral along various electric field lines computed from the potential distribution. By taking into account the localization of trap states in the grain boundaries, the effects on the breakdown voltage of the doping concentration ND, the intergranular trap state density NT, the grain sizes Lg, the disposition of the grain boundaries, and the film thickness tf are investigated. The simulation results show that the impact ionization mechanism is more accelerated in polysilicon than in single-crystalline silicon, and the BV(Lg), BV(ND), BV(NT), and BV(tf) curves are characterized by a succession of descending stair shapes due to the trapping of free carries by trap states contained in grain boundaries that are parallel to the metallurgic junction. By comparing simulation results with experimental data, we select the electron-hole ionization coefficients characterizing our samples: αn∞=1.0×106cm−1, Encrit=5.87×106Vcm−1, αp∞=1.582×106cm−1, and EPcrit=2.036×106Vcm−1. The fit shows that the extracted NT varies from 1.07×1013, 4×1012, and 2×1012cm−2 when the film thickness varies from 250, 350, and 450nm, respectively. These results validate the developed model and confirm that structural and electronic properties of the polycrystalline deposition films are improved during the layer growth.

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process

Localisation of the p-n junction in poly-silicon thin-film diodes on glass by high-resolution cross-sectional electron-beam induced current imaging

High-resolution scanning electron microscope, focused ion beam (FIB) microscope, and electron-beam induced current (EBIC) images are taken on large-grained polycrystalline silicon thin-film diodes on glass. To aid understanding of the plan-view EBIC images obtained, trenches are cut into the diodes in the FIB microscope, and the p-n junction then located and examined in the diode's cross section using high-resolution EBIC. Diffusion of aluminium atoms from the heavily doped emitter region into the base region of the diode along grain boundaries during material fabrication is found to have locally altered the junction's location and therefore alters the EBIC signal in these regions. Using this method allows a fast and easy location of the p-n junction in these diodes, in addition to aiding in the identification of unusual junction deviations which complicate the interpretation of plan-view EBIC images.

Two-dimensional simulation of the effects of grain boundaries on the C–V characteristics of P+N polysilicon diodes

A two-dimensional numerical code is developed to model the effect of grains boundaries (g.b.) on the capacitance–voltage (C–V) characteristics of polysilicon diodes. The test structures are lateral polysilicon P+N diodes where the thickness of the film tf deposited by the low-pressure chemical vapour deposition method is 700 or 450 nm. The P+ and N dopings were performed by ion implantation using, respectively, boron in a dose of 2 × 1015 cm−2 and phosphorus in two doses of 1014 cm−2 for tf = 700 nm and 5 × 1014 cm−2 for tf = 450 nm. Using scanning electron microscopy, the presence of one grain boundary (g.b.) perpendicular to the metallurgic junction and localized at 100 nm of the interface deposition has been observed. In this work, we particularly investigate the effect of this g.b. on the C–V characteristics. The measured C–V characteristics at 100 kHz and 1 MHz show that the frequency effect is more important in the case of the weakly doped film (tf = 700 nm). A determination of the series resistance gives the profile doping concentration: abrupt (ND = 5.5 × 1018 cm−3) for tf = 700 nm and gradual (slope = 5 × 1025 cm−4) for tf = 450 nm.Using the previous experimental parameters in the two-dimensional simulation, we show that the presence of the perpendicular g.b. can reduce by up to 25% the capacitance of the diode and decreases considerably the VRP voltage that corresponds to the realizing–pinning of the electrostatic potential at the first parallel g.b. This effect is more important when the doping is gradual. The fit of the experimental curves gives, in the weak doping case (tf = 700 nm), the position of the first parallel g.b. (LG1 = 37.5 nm) and the density of the inter-granular trap states (NT = 3.2 × 1012 cm−2). On the other hand, when the doping is relatively strong (tf = 450 nm), the fit shows that the C–V characteristic is dominated much more by the doping profile than by the position of the first grain boundary and the density of the inter-granular trap states.

Key role of nanocrystalline feature in porous polycrystalline silicon diodes for efficient ballistic electron emission

The cold electron emission characteristics of nanocrystalline porous polysilicon (PPS) diodes have been investigated for two PPS diodes prepared under different conditions. The origin of the difference in the emission efficiency and electron energy distribution between the two samples is analyzed in relation to the respective photoluminescence properties. The photoluminescence spectrum in the efficient electron emitter consists of red and blue emission bands corresponding to nanocrystalline silicon and interfacial oxide, respectively, while that in the low-efficiency emitter consists only of a blue band. Too much oxidation results in a reduction of the emission efficiency due to increased electron scattering. It is evident that both the formation of nanocrystalline silicon and its appropriate surface oxidation are key issues for obtaining efficient ballistic emission. These results are consistent with the emission model that electrons are accelerated in the PPS layer by multiple tunneling through interfacial oxide barriers between interconnected silicon nanocrystallites.

High-Current Characterization of Polysilicon Diode for Electrostatic Discharge Protection in Sub-Quarter-Micron Complementary Metal Oxide Semiconductor Technology

Polysilicon diodes used in sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies are characterized by transmission line pulse (TLP) measurement to investigate device characteristics in a high-current regime. The second-breakdown current (It2) of the polysilicon diode shows good linear dependence on the device junction perimeter. When the polysilicon diodes are connected in a stacked configuration for reducing parasitic capacitance, the stacked polysilicon diodes show no degradation in electrostatic discharge (ESD) robustness compared with a single polysilicon diode. Such CMOS process-compatible polysilicon diodes have been successfully used as on-chip ESD protection devices for GHz radio-frequency (RF) circuits.

Multiple Lateral Polysilicon Diodes as Temperature Sensors for Chemical Microreaction Systems

Lateral polysilicon P+–N–N+ and P+–P–N+ diodes were fabricated and their reverse current was measured at various temperatures in the range of 50°C to 150°C. The reverse current at a constant bias was characterized and used as a parameter to determine temperature by a method proposed in this work for possible application in a chemical microreaction system. Polysilicon diodes in a series combination of 2 or 3 were also fabricated and their electronic properties such as ON resistance, reverse current and ideality factor were studied. The ON resistance and the ideality factor increased linearly with the number of diodes in series, owing to the effect of the series combination of diodes. The multiple diodes also showed a lower reverse current than the individual single diodes in the series. Hence, it is beneficial to use these multiple diodes as temperature sensors, since they give the least error in temperature determination.

Electron emission characteristics of the porous polycrystalline silicon diode

Abstract It is estimated that a porous polysilicon (PPS) diode with a structure of Au/PPS/n-type Si operates as an efficient stable surface emitting cold cathode. 2.0 μm of an non-doped polysilicon layer is formed on an heavily doped n-type silicon wafer and anodized in a solution of HF (50%):ethanol=1:1 under illumination by a 500 W tungsten lamp from a distance of 20 cm. The electron emission properties of the PPS diode were investigated as a function of anodizing condition such as anodizing current density. The electron emission trajectory was investigated, and it was also demonstrated their good uniformity in the emitting area.

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.

P‐44: Optimization and Characterization of the Porous Poly‐silicon Emitter

AbstractIt is estimated that a porous polysilicon (PPS) diode with a structure of Au/PPS/n‐type Si operates as an efficient stable surface emitting cold cathode. 2.0 μm of an nondoped polysilicon layer is formed on an heavily doped n‐type silicon wafer and anodized in a solution of HF(50%): ethanol = 1: 1 under illumination by a 500 W tungsten lamp from a distance of 20 cm. The electron emission properties of the PPS diode were investigated as a function of anodizing condition. It was found that the electron emission properties depend on the anodizing condition, and the optimum anodizing condition is 10mA/cm2 for 15 seconds. The PPS diode emitter fabricated by using the optimum condition has higher efficiency, lower diode current and higher emission current compared to that of other PPS diode emitter. The electron emission characteristics as a function of ambient pressure and the electron trajectory were also studied. Furthermore, the fluctuation properties of the PPSE was investigated and discussed.

On-chip ESD protection design by using polysilicon diodes in CMOS process

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. This design has been practically applied in a mass-production smart-card IC.

High performance gated lateral polysilicon PIN diodes

This paper investigates the characteristics of high performance lateral polysilicon diodes. Low leakage currents and high ON currents were achieved using a gated PIN diode structure. An independent control gate terminal was placed over the intrinsic region of the diodes to improve the properties of the polysilicon diodes. The addition of the control gate was found to improve both the ON resistance and the leakage current by an order of magnitude. The gated PIN diodes had leakage currents less than 0.05 pA μm −1 width at 5 V of reverse bias, and ON resistance less than 1 MΩ μm −1 width for an intrinsic region length of 2 μm. A gated PIN diode model is presented that models the diode as an ideal diode in series with a thin film transistor. This model is used to explain the impact of the control gate on the ON resistance and the leakage current of the gated PIN lateral polysilicon diodes.

Mechanism of efficient and stable surface-emitting cold cathode based on porous polycrystalline silicon films

It is demonstrated that a porous polysilicon (PPS) diode with a structure of Au/PPS/n-type Si operates as an efficient stable surface-emitting cold cathode. 1.5 μm of an nondoped polysilicon layer is formed on an n-type (100) silicon wafer and anodized in a solution of HF (50%): ethanol=1:1 at a current density of 10 mA/cm2 for 30 s under illumination by a 500 W tungsten lamp from a distance of 20 cm. Subsequently, a PPS layer is oxidized in a rapid thermal oxidation furnace for 1 h at a temperature of 700 °C. A semitransparent thin Au film (about 10 nm thick) is deposited onto the PPS layer as a positive electrode and an ohmic contact is formed at the back side of the silicon wafer as a negative electrode. When a positive bias is applied to the Au electrode in vacuum, the diode uniformly emits electrons. No electron emission is observed in the negatively biased region. Emission current is about 10−4 A/cm2 at a 20 V bias. It is further demonstrated that electrons are quasiballistically emitted from a PPS diode due to a significantly reduced electron scattering in the PPS layer. As a result, the diode can emit fluctuation-free stable electron emission. The simplified model of emission and energy distribution of electrons are proposed and it can explain the experimental results.