Polysilicon Devices Research Articles

High-performance tin perovskite transistors through formate pseudohalide engineering

The lack of high-performance p-type semiconducting materials hinders the integration of complementary metal-oxide semiconductors with well-established n-type metal-oxide counterparts. Although tin halide perovskites are promising p-type material candidates, their practical implementation is hindered by excessive hole concentrations and difficulties in precisely controlling crystallization, which leads to poor device performance and yield. In this paper, we propose a formate pseudohalide engineering method to overcome these issues and demonstrate high-performance tin perovskite thin-film transistors (TFTs). The incorporation of formate anion greatly suppresses the vacancy defects at the surfaces of the perovskite films with an increase in crystallinity and grain size. This reduces the hole concentration and eliminates the dependence on the addition of excessive tin fluoride for hole suppression. Hence, high-performance TFTs with a high average field-effect hole mobility of 57.34 cm2 V−1 s−1 and on/off current ratios surpassing 108 can be achieved, approaching p-channel low-temperature polysilicon devices.

High-Sensitivity CMOS-Integrated Floating Gate-Based UVC Sensors.

We report on novel UVC sensors based on the floating gate (FG) discharge principle. The device operation is similar to that of EPROM non-volatile memories UV erasure, but the sensitivity to ultraviolet light is strongly increased by using single polysilicon devices of special design with low FG capacitance and long gate periphery (grilled cells). The devices were integrated without additional masks into a standard CMOS process flow featuring a UV-transparent back end. Low-cost integrated UVC solar blind sensors were optimized for implementation in UVC sterilization systems, where they provided feedback on the radiation dose sufficient for disinfection. Doses of ~10 µJ/cm2 at 220 nm could be measured in less than a second. The device can be reprogrammed up to 10,000 times and used to control ~10-50 mJ/cm2 UVC radiation doses typically employed for surface or air disinfection. Demonstrators of integrated solutions comprising UV sources, sensors, logics, and communication means were fabricated. Compared with the existing silicon-based UVC sensing devices, no degradation effects that limit the targeted applications were observed. Other applications of the developed sensors, such as UVC imaging, are also discussed.

Polysilicon devices as a highly compatible ESD protection with modulable voltage and low capacitance

The electronic circuits fabricated in a variety of technologies for different applications are all vulnerable to the electrostatic discharge (ESD) event. In this paper, polysilicon devices are investigated as ESD protection because of the noticeable advantages such as compatibility with several technologies, low parasitical capacitance, and little noise coupling. By forming the p-i-n diode in the polysilicon layer and stacking them together, the single polysilicon diode (SPD) and cascaded polysilicon diode (CasPD) are implemented in the 0.35 [Formula: see text] high voltage diffusion process. Through DC IV/CV, transmission line pulse (TLP), and zipping test, the CasPD presents as ESD protection for an S-band RF power amplifier, with high process-compatibility, modulable voltage, low leakage current and parasitic capacitance.

A computational study of the effect of bond pad thickness on the polysilicon piezoresistivity due to wafer level probing

Polysilicon is an integral part of many devices in all CMOS processes. Circuit Under Pad (CUP) devices are required to have consistent and accurate electrical performance just like any other device. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options (METMID and METTHK) on a polysilicon resistor placed under the bond pad. Wafer level probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance (piezoresistivity) of a polysilicon resistor which was placed underneath the bond pads. A commercial finite element analysis software (Comsol Multiphysics) was used to predict the stress distribution in the polysilicon device, followed by experimental validation of the electrical resistance. It was observed that the bond pad thickness can influence the residual stress which in turn causes a change in resistance after wafer level probing. However, for each bond pad thickness, multiple probe insertions did not significantly change the resistance of the device placed under the bond pad.

Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification

We describe the physics of the turn-off mechanism in source-gated transistors (SGTs), which is distinct from that of conventional thin-film field-effect transistors and allows significantly lower off currents, particularly in depletion-mode devices. The “n-type” SGT enters its off state when the potential applied across the semiconductor layer is decreased to low positive values or made negative through the applied gate bias, thus impeding charge injection from the source contact. Measurements on polysilicon devices were supported with TCAD simulations using Silvaco Atlas. Alongside the other known benefits of SGTs, including low saturation voltage, tolerance to process variations, and high intrinsic gain, the ability to efficiently block current at high negative gate voltages suggests that these devices would be ideal elements in emerging thin-film power management and rectification circuits.

A Programmable Sustaining Amplifier for Flexible Multimode MEMS-Referenced Oscillators

This paper presents a programmable single-chip sustaining amplifier for MEMS-referenced oscillators. The chip integrates a low-noise amplifier, variable-gain amplifiers (VGAs), band-pass filters (BPFs), all-pass filters (APFs), automatic level control, and output buffers. It also contains a second signal path for background cancellation, i.e., eliminating the effect of electrical feedthrough capacitance of the MEMS resonator. Important parameters of each circuit block (e.g., VGA gain, BPF center frequency and quality factor ( $Q$ ), APF phase shift, and so on.) can be set using bias currents, thus enabling fine-grained control over the overall transfer function. The amplifier was designed and fabricated in $0.5~\mu \text{m}$ CMOS. The chip was integrated with board-level current DACs (programmable via an I2C bus) and tested inside a vacuum chamber with various polysilicon (poly-Si) and single crystal (SC-Si) silicon comb-drive MEMS devices with resonant frequencies in the 10–90 kHz range. Oscillators referenced to a high- $Q$ (~13 000) SC-Si device had 20 dBc/Hz lower close-in phase noise (at 10 Hz) than those referenced to the low- $Q$ (~320) poly-Si device. Experimental results highlight advantages of the design, including automatic mode selection, background cancellation, control of feedback phase to optimize phase noise, and frequency locking to an external reference.

A dependency of emission efficiency of poly-silicon light-emitting device on avalanching current

A novel polysilicon light emitting device (LED) was realized in a standard complementary metal oxide semiconductor (CMOS) process that is based on a p-n junction reverse bias configuration. This LED can emit visible light based on the reverse bias p-n junctions in the dark. The central emitting doped structure element of this LED is n+-p-n+-p-n+ stacked layout, which is similar to two reverse bias p-n junctions and two forward bias p-n junctions connected in series. The device mechanism for the visible light emitting process is defined by means of an avalanche breakdown process that occurs between the highly doped n+ region and the lightly doped p region in the reverse bias p-n junctions. By using hot carriers generated in avalanche process, the emission spectrum from the device exhibits a wide spectrum whose wavelength range is from 400 nm to 900 nm at an operating voltage of 16 V. We compare the designed light intensities at the different wavelengths in other to obtain the dependency of the light emission at various wavelengths under different currents conditions. From the experimental observations, and based on the calculation of the quantum efficiency and power conversion efficiencies as related to the light emission, we confirmed that this particular LED has a better efficiency than three-terminal gated diode. The silicon light source could find some applications in on-chip optical interconnect and in electro-optical conversions in future all-silicon integrated photonic circuitry.

Microelectromechanical Systems from Aligned Cellulose Nanocrystal Films.

Microelectromechanical systems (MEMS) have become a ubiquitous part of a multitude of industries including transportation, communication, medical, and consumer products. The majority of commercial MEMS devices are produced from silicon using energy-intensive and harsh chemical processing. We report that actuatable standard MEMS devices such as cantilever beam arrays, doubly clamped beams, residual strain testers, and mechanical strength testers can be produced via low-temperature fabrication of shear-aligned cellulose nanocrystal (CNC) films. The devices had feature sizes as small as 6 μm and anisotropic mechanical properties. For 4 μm thick doubly clamped beams with the CNC aligned parallel to the devices' long axes, the Young's moduli averaged 51 GPa and the fracture strength averaged 1.1 GPa. These mechanical properties are within one-third of typical values for polysilicon devices. This new paradigm of producing MEMS devices from CNC extracted from waste biomass provides the simplicity and tunability of fluid-phase processing while enabling anisotropic mechanical properties on the order of those obtained in standard silicon MEMS.

Light emission from a poly-silicon device with carrier injection engineering

Development work was conducted on N+PN+PN+ Poly silicon light-emitting devices which are compatible with silicon-based integrated circuit technology. We discuss the emission characteristics of visible light by a monolithically integrated Poly-Si diode under reverse bias. With the structure of modified PN junctions, the carriers injection occurs through silicon slabs of only a few nanometer thick. The dominant role of non-radiative recombination at the N+ and P+ contacts is diminished by confining the injected carriers around the PN junction’s interface in which avalanche takes place. The current-dependent optical radiation presents a broad spectrum in the 400- to 900-nm range. Although the emission efficiency is low due to silicon’s indirect bandgap, it is advantageous to utilize these devices in all-silicon optoelectronic integrated circuits (OIC’s).

Characterization of Oxide-Coated Polysilicon Disk Resonator Gyroscope Within a Wafer-Scale Encapsulation Process

In this paper, we present the fabrication and test results of an oxide-coated polysilicon disk resonator gyroscope in a wafer-scale encapsulation process. We demonstrate the effects of an oxide coating on the device structure and the key performance parameters of resonant-based sensors, such as the temperature coefficient of frequency and quality factor ( $Q$ ). Results from the as-fabricated device show that a thin oxide coating reduces the surface roughness of a fully encapsulated device by $10\times $ , compared with a polysilicon device without the oxide coating. This increases the uniformity across the wafer, providing higher process yield. The open-loop rate measurement mode reveals an angle random walk of 0.18°/ $\surd $ hr and a bias instability of 1.43°/hr. [2015-0124]

Oxide driven strength evolution of silicon surfaces

Previous experiments have shown a link between oxidation and strength changes in single crystal silicon nanostructures but provided no clues as to the mechanisms leading to this relationship. Using atomic force microscope-based fracture strength experiments, molecular dynamics modeling, and measurement of oxide development with angle resolved x-ray spectroscopy we study the evolution of strength of silicon (111) surfaces as they oxidize and with fully developed oxide layers. We find that strength drops with partial oxidation but recovers when a fully developed oxide is formed and that surfaces intentionally oxidized from the start maintain their high initial strengths. MD simulations show that strength decreases with the height of atomic layer steps on the surface. These results are corroborated by a completely separate line of testing using micro-scale, polysilicon devices, and the slack chain method in which strength recovers over a long period of exposure to the atmosphere. Combining our results with insights from prior experiments we conclude that previously described strength decrease is a result of oxidation induced roughening of an initially flat silicon (1 1 1) surface and that this effect is transient, a result consistent with the observation that surfaces flatten upon full oxidation.

Observation of nanoscale adhesion, friction and wear between ALD Al2O3 coated silicon MEMS sidewalls

We report a novel investigation of the tribological properties of aluminum oxide (Al2O3) when it is used as protective coating on the sidewalls of microelectromechanical systems (MEMS). By using an in-house built optical displacement measurement system, we were able to measure the on-chip displacements with an unprecedented resolution of 2 nm. This corresponds to 2 nN and 9 nN force resolution, respectively, depending on whether an adhesion or a friction sensor MEMS device was used for the measurement. Al2O3 was deposited on the vertical etched sidewalls using atomic layer deposition (ALD). All tests were carried out in ambient conditions. The same tests carried out on uncoated polysilicon devices were not reproducible due to stiction, which sometimes prevented the interacting surfaces from moving once contact was made. The higher adhesion of silicon was also found to hinder the mobility of the slider. In the ALD-coated devices, we observed increasing adhesion after 50000 repeated contacts. We attribute this increase to the accumulation of aluminum hydroxide debris produced by the reaction with moisture in the environment. We also investigated the long-term effect of friction on the coated silicon sidewalls. The dissipated energy decreases, with a minimum lateral force occurring around the 1000th cycle. After 1000 cycles, the lateral displacement decreases, suggesting an additional lateral dragging force caused by the interaction between a mixture of aluminum hydroxides and water. However, the small overall amount of debris produced during the friction test indicates the outstanding characteristic of Al2O3 as a protective coating for MEMS that use contacting or sliding interfaces.

Finite Element Analysis of the Vertical Levitation Force in an Electrostatic MEMS Comb Drive Actuator

A vertical levitation electrostatic comb drive actuator was manufactured for the purpose of measuring piezoelectric coefficients in small-scale materials and devices. Previous modelling work on comb drive levitation has focussed on control of the levitation in standard poly-silicon devices in order to minimize effects on lateral modes of operation required for the accelerometer and gyroscope applications. The actuator developed in this study was manufactured using a 20 μm electroplated Ni process with a 25 μm trench created beneath the released structure through chemical wet etching. A finite element analysis using ZINC was used to model electrostatic potential around a cross section of one static and one movable electrode, from which the net levitation force per unit electrode was calculated. The model was first verified using the electrode geometry from previously studied systems, and then used to study the variation of force as a function of decreasing substrate-electrode distance. With the top electrode surfaces collinear the calculated force density is 0.00651 ϵ0V2Mμm−1, equivalent to a total force for the device of 36.4 μN at an applied voltage of VM=100 V, just 16% larger than the observed value. The measured increase in force with distance was smaller than predicted with the FEA, due to the geometry of the device in which the electrodes at the anchored ends of the supporting spring structure displace by a smaller amount than those at the centre.

Crystallographic effects in modeling fundamental behavior of MEMS silicon resonators

This paper presents the effects of silicon crystal properties on fundamental behavior of MEMS resonators. MEMS resonators are commonly built from single crystal silicon with proven long-term stability. Frequency and quality factor (Q) of silicon resonators, however, depend on the silicon crystal orientation and its interplay with the resonance mode. It is experimentally shown that Q of resonators can vary up to 25% with change in crystal orientation. Anisotropy also causes a split in frequencies of degenerate mode pairs of disk resonators, splitting also occurs in nominally isotropic polysilicon devices where theoretically not expected. In this paper, we model resonators based on crystallographic properties to predict and explain these experimental results. Tuning forks quality factor dependence on orientation in (100) and (111) wafers as well as frequency splitting of disk resonators is examined. Incorporating appropriate silicon crystal elasticity into finite-element modeling and accounting for geometric implications of these resonators we demonstrate that the frequency splitting and quality factor of those devices can be accurately predicted.

TCR Sign Variation of Surface Micromachined Polysilicon Resistor under Joule Self-Heating

This work reports the sign variation of temperature coefficient of surface micromachined polysilicon resistor due to Joule self-heating effect. It was found that the sign of temperature coefficient of polysilicon resistor with initial negative temperature coefficient value varies two times from negative to positive and then from positive to negative with the consumed power increasing, while the sign of the temperature coefficient of polysilicon resistor with initial positive value only changes once to negative. The experiment results indicate that much more attention should be paid to the temperature coefficient of polysilicon resistor for the surface micromachined electrothermal polysilicon devices.

Polysilicon Source-Gated Transistors for Mixed-Signal Systems-on-Panel

The performance benefits of using source-gated transistors (SGTs) in large-area analog electronic circuits are examined by both experiments and numerical simulations. As one of the key blocks in analog electronics, the current mirror circuit is taken as an example in the investigation. A comparison of current mirrors implemented with standard field effect transistors (FETs) and SGTs shows that the SGT based circuits can operate at a lower voltage and has larger output dynamic range for a given device geometry. The results are explained in relation to the saturation mechanisms of the SGT and are supported by experimental measurements of polysilicon devices.

Characterization of frequency tuning using focused ion beam platinum deposition

This paper presents and characterizes focused ion beam (FIB) platinum (Pt) deposition as a novel frequency tuning method for micromechanical resonators. FIB Pt deposited tuning was performed at room temperature and in contrast to other reported methods, frequency changes were achieved without any device failure. To perform the tuning, Pt was deposited on a 13 µm× 5 µm surface area at the free end of 3C silicon carbide (SiC) and polysilicon cantilever resonators in thicknesses ranging from 0.5 µm to 2.6 µm. To determine the amount of tuning, the resonant frequency of SiC and polysilicon devices was measured before and after Pt deposition. Frequency measurements performed before Pt deposition found that SiC resonators operated at higher resonant frequencies and quality (Q)-factors than their polysilicon counterparts. Measurements after Pt deposition on SiC and polysilicon resonators confirmed the predicted maximum frequency change of −15.5% made by FEM simulations and analytical modelling. Due to their lower mass, polysilicon resonators showed a larger frequency change than their SiC counterparts. A Q-factor decrease was observed for SiC and polysilicon resonators due to thermoelastic damping associated with the deposited Pt and surface contamination.

ADVANCEMENTS IN NANOELECTRONIC SONOS NONVOLATILE SEMICONDUCTOR MEMORY (NVSM) DEVICES AND TECHNOLOGY

This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.

Surface roughness measurements of micromachined polycrystalline silicon films

The characteristics of the materials and surfaces in microelectromechanical systems (MEMS) and microsystems technology (MST) profoundly affect the performance, reliability, and wear of MEMS and MST devices. It is critical to measure the properties of surfaces that are in contact during microstructure movement, such as the underside of a MEMS gear and the underlying substrate. However, contacting surfaces are usually inaccessible unless the MEMS device is broken and removed from the substrate. This paper presents a nondestructive method for characterizing commercially fabricated surface micromachined polycrystalline silicon (polysilicon) devices. Microhinged flaps were designed that enable access to the upper surface, the part of a structural layer deposited last; the lower surface, the part of a structural layer deposited first; and the underlying substrate. Due to the susceptibility of surface-micromachined MEMS to adhesion failures, the surface roughness is a key parameter for predicting device behavior. Using the microhinged flaps, the RMS surface roughness for polycrystalline surfaces was measured and indicated that the upper surfaces were 3.5–6.4 times rougher than the lower surfaces. The difference in the surface roughness for the upper surface, which is easily accessed and the one most commonly characterized, and that for the lower surface reveals the importance of characterizing contacting surfaces in MEMS and MST devices.

A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS

The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.