Polygon Rasterization Research Articles

A systematic scheme to maintain multiple characteristics for effective polygon rasterization

Polygon characteristics, including area, shape, and topology, may be lost during rasterization, leading to inaccurate analyses. Maintaining multiple characteristics remains a challenging multi-objective optimization problem. This study introduces improved strategies for flexibly maintaining multiple characteristics (ISMMC). Errors related to area (A), shape (S), and topology (T) are addressed using six prioritized sequences: AST, ATS, TAS, TSA, STA, and SAT, where the order of the letters denotes the sequence of error correction. The importance (I) of land-use types (LUT) is also considered when developing a strategy based on the TSA (ITSA) that maintains characteristics for important LUTs. The ISMMC achieved a total improved accuracy (IA) of ≥0.05 for 98.67% of 150 tested cases. The STA, SAT, TAS, and TSA yielded the highest area, shape, topological, and total accuracies. The STA achieved a summed AI increase ≥20.36% compared to the existing version. The runtime was ≥85.46 times the scanline runtime, and the threshold cell size (≤50 m) balanced the IA and runtime. The ITSA improved accuracy by 83.33% and 6.67% of solutions when preferentially maintaining one or two important LUTs, outperforming the existing STA. Overall, these developments improve accuracy with flexibility in rasterization results and subsequent raster applications.

BakedAvatar: Baking Neural Fields for Real-Time Head Avatar Synthesis

Synthesizing photorealistic 4D human head avatars from videos is essential for VR/AR, telepresence, and video game applications. Although existing Neural Radiance Fields (NeRF)-based methods achieve high-fidelity results, the computational expense limits their use in real-time applications. To overcome this limitation, we introduce BakedAvatar , a novel representation for real-time neural head avatar synthesis, deployable in a standard polygon rasterization pipeline. Our approach extracts deformable multi-layer meshes from learned isosurfaces of the head and computes expression-, pose-, and view-dependent appearances that can be baked into static textures for efficient rasterization. We thus propose a three-stage pipeline for neural head avatar synthesis, which includes learning continuous deformation, manifold, and radiance fields, extracting layered meshes and textures, and fine-tuning texture details with differential rasterization. Experimental results demonstrate that our representation generates synthesis results of comparable quality to other state-of-the-art methods while significantly reducing the inference time required. We further showcase various head avatar synthesis results from monocular videos, including view synthesis, face reenactment, expression editing, and pose editing, all at interactive frame rates on commodity devices. Source codes and demos are available on our project page.

Parallel multi-view polygon rasterization for 3D light field display.

Three-dimensional (3D) light field displays require samples of image data captured from a large number of regularly spaced camera images to produce a 3D image. Generally, it is inefficient to generate these images sequentially because a large number of rendering operations are repeated in different viewpoints. The current 3D image generation algorithm with traditional single viewpoint computer graphics techniques is not sufficiently well suited to the task of generating images for the light field displays. A highly parallel multi-view polygon rasterization (PMR) algorithm for 3D multi-view image generation is presented. Based on the coherence of the triangular rasterization calculation among different viewpoints, the related rasterization algorithms including primitive setup, plane function, and barycentric coordinate interpolation in the screen space are derived. To verify the proposed algorithm, a hierarchical soft rendering pipeline with GPU is designed and implemented. Several groups of images of 3D objects are used to verify the performance of the PMR method, and the correct 3D light field image can be achieved in real time.

A topology-preserving polygon rasterization algorithm

ABSTRACTConventional algorithms for polygon rasterization are typically designed to maintain non-topological characteristics. Consequently, topological relationships, such as the adjacency between polygons, may also be lost or altered, creating topological errors. This paper proposes a topology-preserving polygon rasterization algorithm to avoid topological errors. Four types of topological error may occur during polygon rasterization. The algorithm starts from an initial polygon rasterization and uses a set of preserving strategies to increase topological accuracy. The count of the four types of error measures the topological errors of the conversion. Topological accuracy is summarized as 1 minus the ratio of actual topological errors to the total number of possible error cases. When applied to a land-use dataset with a data volume of 128 MB, 127,836 polygons, and extending 1352 km2, the algorithm achieves a topological accuracy of more than 99% when raster cell size is 30 m or smaller (100% for 5 and 10 m). The effects of cell size, polygon shape, and number of iterations on topological accuracy are also examined.

A Parallel Scheme for Large‐scale Polygon Rasterization on CUDA‐enabled GPUs

AbstractThis research develops a parallel scheme to adopt multiple graphics processing units (GPUs) to accelerate large‐scale polygon rasterization. Three new parallel strategies are proposed. First, a decomposition strategy considering the calculation complexity of polygons and limited GPU memory is developed to achieve balanced workloads among multiple GPUs. Second, a parallel CPU/GPU scheduling strategy is proposed to conceal the data read/write times. The CPU is engaged with data reads/writes while the GPU rasterizes the polygons in parallel. This strategy can save considerable time spent in reading and writing, further improving the parallel efficiency. Third, a strategy for utilizing the GPU's internal memory and cache is proposed to reduce the time required to access the data. The parallel boundary algebra filling (BAF) algorithm is implemented using the programming models of compute unified device architecture (CUDA), message passing interface (MPI), and open multi‐processing (OpenMP). Experimental results confirm that the implemented parallel algorithm delivers apparent acceleration when a massive dataset is addressed (50.32 GB with approximately 1.3 × 108 polygons), reducing conversion time from 25.43 to 0.69 h, and obtaining a speedup ratio of 36.91. The proposed parallel strategies outperform the conventional method and can be effectively extended to a CPU‐based environment.

Data decomposition method for parallel polygon rasterization considering load balancing

It is essential to adopt parallel computing technology to rapidly rasterize massive polygon data. In parallel rasterization, it is difficult to design an effective data decomposition method. Conventional methods ignore load balancing of polygon complexity in parallel rasterization and thus fail to achieve high parallel efficiency. In this paper, a novel data decomposition method based on polygon complexity (DMPC) is proposed. First, four factors that possibly affect the rasterization efficiency were investigated. Then, a metric represented by the boundary number and raster pixel number in the minimum bounding rectangle was developed to calculate the complexity of each polygon. Using this metric, polygons were rationally allocated according to the polygon complexity, and each process could achieve balanced loads of polygon complexity. To validate the efficiency of DMPC, it was used to parallelize different polygon rasterization algorithms and tested on different datasets. Experimental results showed that DMPC could effectively parallelize polygon rasterization algorithms. Furthermore, the implemented parallel algorithms with DMPC could achieve good speedup ratios of at least 15.69 and generally outperformed conventional decomposition methods in terms of parallel efficiency and load balancing. In addition, the results showed that DMPC exhibited consistently better performance for different spatial distributions of polygons.

Large-scale spatial data processing on GPUs and GPU-accelerated clusters

The massive data parallel computing power provided by inexpensive commodity Graphics Processing Units(GPUs) makes large-scale spatial data processing on GPUs and GPU-accelerated clusters attractive from both a research and practical perspective. In this article, we report our works on data parallel designs of spatial indexing, spatial joins and several other spatial operations, including polygon rasterization, polygon decomposition and point interpolation. The data parallel designs are further scaled out to distributed computing nodes by integrating single-node GPU implementations with High-Performance Computing (HPC) toolset and the new generation in-memory Big Data systems such as Cloudera Impala. In addition to introducing GPGPU computing background and outlining data parallel designs for spatial operations, references to individual works are provided as a summary chart for interested readers to follow more details on designs, implementations and performance evaluations.

Non‐Linear Beam Tracing on a GPU

AbstractBeam tracing combines the flexibility of ray tracing and the speed of polygon rasterization. However, beam tracing so far only handles linear transformations; thus, it is only applicable to linear effects such as planar mirror reflections but not to non‐linear effects such as curved mirror reflection, refraction, caustics and shadows. In this paper, we introduce non‐linear beam tracing to render these non‐linear effects. Non‐linear beam tracing is highly challenging because commodity graphics hardware supports only linear vertex transformation and triangle rasterization. We overcome this difficulty by designing a non‐linear graphics pipeline and implementing it on top of a commodity GPU. This allows beams to be non‐linear where rays within the same beam do not have to be parallel or intersect at a single point. Using these non‐linear beams, real‐time GPU applications can render secondary rays via polygon streaming similar to how they render primary rays. A major strength of this methodology is that it naturally supports fully dynamic scenes without the need to pre‐store a scene database. Utilizing our approach, non‐linear ray tracing effects can be rendered in real‐time on a commodity GPU under a unified framework.

Rasterizing complex polygons without tessellations

Rasterization of polygons is a basic operation in computer graphics systems, representing the last and most time-consuming step in the visualization process. Therefore, the development of simple, efficient, and general polygon rasterization techniques is of prime interest. In this paper, we describe a new algorithm for this purpose, inspired on the ideas of the geometric modeling based on simplicial chains [Computer and Graphics 5 (1998) 611]. This algorithm is valid for any kind of polygon, is robust and extremely simple, and can be easily implemented in hardware. A similar approach can be used for the problem of polihedra voxelization in 3D.

Optimal static 2-dimensional screen subdivision for parallel rasterization architectures

Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated circuits, or developing designs which use an array of processors. Pixel-Planes 1–5 and PixelFlow ‡ ‡ Pixel-Planes 1–5 and PixelFlow were developed at the University of North Carolina. are examples of architectures which use an array of pixel processors for rasterization. Early generations of Pixel-Planes attempted to make these arrays as large as the display providing one processor for each display pixel. Later generations improved performance by grouping processors into multiple smaller arrays, subdividing the screen into sections of a corresponding size and having the arrays independently process the screen subdivisions. This paper describes simulations which were performed to determine the optimum size subdivision for a graphics computer which uses Pixel-Planes type parallelism, i.e. static two dimensional screen subdivision parallel polygon rasterization. We then develop a mathematical approach to determining the optimal subdivision size and show that it agrees well with the experimental data. For special purpose architectures we show that the optimal size depends not only on the polygon size but also on the silicon area consumed by the rasterizer overhead. The mathematical approach can be directly applied to special purpose architectures, and we show how it can be modified for use in analyzing algorithms developed for general purpose architectures such as the Intel Touchstone or Paragon, or the Thinking Machines CM-5.

A low-power high performance polygon renderer for computer graphics

Polygon rasterization is one of the most computational and memory intensive operations in computer graphics. In this paper, we present a low-power, real-time hardware design for this task. The system is resolution-independent by configuring different numbers of render engines in a 2-dimensional array. Using an array configuration of 16 render engines for a 512×512-pixel display, a peak performance of up to 3.4 million Gouraud-shaded polygons/sec is achievable. Total power consumption, depending on the polygon throughput, ranges between 17 mW to 133 mW at 1.5 V operation. A format for transmitting polygon information is proposed at a typical bandwidth of 4 Mbps, suitable for wireless transmission. This screen and format configurable design has potential application in portable, wireless head-mounted displays for virtual reality systems.

A parallel algorithm for polygon rasterization

A parallel algorithm for the rasterization of polygons is presented that is particularly well suited for 3D Z-buffered graphics implementations. The algorithm represents each edge of a polygon by a linear edge function that has a value greater than zero on one side of the edge and less than zero on the opposite side. The value of the function can be interpolated with hardware similar to hardware required to interpolate color and Z pixel values. In addition, the edge function of adjacent pixels may be easily computed in parallel. The coefficients of the "Edge function" can be computed from floating point endpoints in such a way that sub-pixel precision of the endpoints can be retained in an elegant way.