Polycrystalline ZnO Thin Film Transistors Research Articles

Effects of annealing temperature on the electrical characteristics of Li–N co-doped polycrystalline ZnO thin film transistors

The effects of annealing temperature on the electrical characteristics of Li–N co-doped ZnO (ZnO:(Li,N)) thin film transistors (TFTs) were studied in this paper. ZnO:(Li,N) active layers were deposited on SiO2/p-type Si substrates by radio frequency magnetron sputtering. After thermal annealing treatment, ZnO:(Li,N) films exhibited an average transparency over 85% in the visible region. In addition, the microstructure and morphology of the ZnO:(Li,N) films were investigated by X-ray diffraction and scanning electron microscopy, confirming the polycrystalline nature and the grain size. The mechanism on the electrical characteristics transition induced by the annealing temperature was also proposed. Finally, thin film transistors incorporating sputtered ZnO:(Li,N) as the active layers exhibited the superior performance; specifically, a high saturation mobility of 33.6 cm2/V s, a suitable threshold voltage of −6 V and a large on/off current ratio of 1.1 × 108.

Radiation-Hard ZnO Thin Film Transistors

We report effects for up to 100 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) gamma-ray exposure on polycrystalline ZnO thin film transistors (TFTs) deposited by two different techniques. The radiation related TFT changes, either with or without electrical bias during irradiation, are primarily a negative VON shift and a smaller VT shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ~ - 2.5 V and ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ~ - 1.5 V for 100 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) exposure). Field-effect mobility remains nearly unchanged. Both, VON and VT shifts are nearly completely removed by annealing at 200°C for 1 minute and some recovery is seen even at room temperature. We find that our ZnO TFTs are insensitive to electrical bias during irradiation; that is, unbiased measurements are useful worst case test results. To the best of our knowledge, these are the most radiation-hard thin film transistors reported to date.

Origin of Oxygen-Induced Abnormal Hump in Bottom-Gated Polycrystalline Zinc Oxide Thin Film Transistors

In this paper, we investigate the origin of abnormal hump after O2 annealing in bottom-gated polycrystalline ZnO thin film transistors (TFTs). The channel width dependency and X-ray diffraction (XRD) analysis show that the hump is not related with the parasitic edge or highly conductive upper layer by the superior crystal quality to channel/gate oxide interface. It is generally known that there is the grain boundary potential barrier (GBPB) caused by the intrinsic point defects such as Znix, VOx and VZnx localized in the grain boundary of ZnO film. X-ray photoelectron spectroscopy (XPS) and The room temperature photoluminescence (RTPL) analysis reveals that the thermal annealing in O2 gas reduces GBPB near ZnO surface forming the additional neutral zinc oxide lattice by the chemical interaction of defects. That is, the oxygen-induced hump is well explained by the reduced GBPB near ZnO surface, which is also supported by the clean transfer curve of ZnO TFTs with floating Schottky contact on the back side of the channel.

Modeling of polycrystalline ZnO thin-film transistors with a consideration of the deep and tail states

We report a model of the carrier transport and the subgap density of states in a polycrystalline ZnO film for simulating a polycrystalline ZnO thin film transistor. This simple model considering the deep and the band tail states reproduces well the characteristics of polycrystalline ZnO thin film transistors. Furthermore, using the developed model, we study the effects of defect parameters on the electrical performances of the polycrystalline ZnO thin film transistors.

Active-layer Thickness Effects Related to the Threshold Voltage and Mobility Degradation in Poly-crystalline ZnO Thin-Film Transistors

Active-layer Thickness Effects Related to the Threshold Voltage and Mobility Degradation in Poly-crystalline ZnO Thin-Film Transistors

Modeling of grain boundary barrier modulation in ZnO invisible thin film transistors

We model grain boundaries (GBs) for polycrystalline ZnO thin film transistors (TFTs). Experimental result shows a non-linear increase of drain current and gradual enhancement of field effect mobility with increasing gate bias. Our initial single GB model was unable to explain the experimentally obtained results, where we considered the peak defect distribution at the mid gap. Realizing from the experimentally obtained results, we remodeled the grain boundary considering the peak distribution close to the conduction band, which then better replicates the experimental observation. We describe here the transfer characteristic of experimental ZnO TFT in linear region with calculated potential profiles. Appropriate grain boundary modeling signifies that the slower decrease in potential barrier in grain boundary with applied gate voltage is responsible for such non-linear changes in drain current and gradual enhancement of mobility.

Modeling and simulation of polycrystalline ZnO thin-film transistors

Thin-film transistors (TFTs) made of transparent channel semiconductors such as ZnO are of great technological importance because their insensitivity to visible light makes device structures simple. In fact, there have been several demonstrations of ZnO TFTs achieving reasonably good field effect mobilities of 1–10 cm2/V s, but the overall performance of ZnO TFTs has not been satisfactory, probably due to the presence of dense grain boundaries. We modeled grain boundaries in ZnO TFTs and performed simulation of a ZnO TFT by using a two-dimensional device simulator in order to determine the grain boundary effects on device performance. Polycrystalline ZnO TFT modeling was started by considering a single grain boundary in the middle of the TFT channel, formulated with a Gaussian defect distribution localized in the grain boundary. A double Schottky barrier was formed in the grain boundary, and its barrier height was analyzed as a function of defect density and gate bias. The simulation was extended to TFTs with many grain boundaries to quantitatively analyze the potential profiles that developed along the channel. One of the main differences between a polycrystalline ZnO TFT and a polycrystalline Si TFT is that the much smaller nanoscaled grains in a polycrystalline ZnO TFT induces a strong overlap of the double Schottky barriers with a higher activation energy in the crystallite and a lower barrier potential in the grain boundary at subthreshold or off-state region of its transfer characteristics. Through the simulation, we were able to estimate the density of total trap states localized in the grain boundaries for polycrystalline ZnO TFT by determining the apparent mobility and grain size in the device.