Polycrystalline Si Thin-film Transistors Research Articles

(Invited) Hydrogenated Polycrystalline In2O3 (In2O3:H) Thin-Film Transistor with High Mobility Exceeding 100 cm2V−1s−1 Via Solid-Phase Crystallization

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μ FE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µ FE = 139.2 cm2V−1s−1. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future electronic applications.

High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μFE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µFE = 139.2 cm2V−1s−1, a subthreshold swing of 0.19 Vdec−1, and a threshold voltage of 0.2 V. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future transparent or flexible electronics applications.

Origin of Spontaneous Degradation of Flexible Poly-Si TFTs After Dynamic Bending

The origin of an abnormal spontaneous degradation of low-temperature polycrystalline Si (LTPS) thin-film transistors (TFTs) is investigated. After being subjected to dynamic bending stress, LTPS TFTs will continuously degrade when stored in a normal condition. Studies have shown that the interaction between the sensitive area of the TFTs and the O2 in ambient environment causes the spontaneous degradation. Defects at the gate oxide/channel interface generated by mechanical stress continuously capturing electrons with the help of oxygen is regarded as the origin of spontaneous degradation. In contrast, moisture in air can effectively suppress spontaneous degradation by reacting with the above defects to form relatively stable atom groups.

Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels.

Spontaneous Degradation of Flexible Poly-Si TFTs Subject to Dynamic Bending Stress

An abnormal spontaneous degradation of polycrystalline Si thin-film transistors (TFTs) subject to dynamic bending stress is reported. Dynamic mechanical bending along either the channel-width or length direction causes degradation in flexible low-temperature polycrystalline Si TFTs, such as on-state current increase and threshold voltage positive shift. However, after the mechanical stress is removed, TFTs stored in a normal ambient continue to degrade spontaneously, with similar degradation behaviors. The amount of spontaneous degradation can be larger than the mechanical bending-induced degradation and is the most significant for a moderate number of bending cycles. The spontaneous degradation is a new challenge to TFT reliability under mechanical stress.

Solution-Based Fabrication of Polycrystalline Si Thin-Film Transistors from Recycled Polysilanes.

Currently, research has been focusing on printing and laser crystallization of cyclosilanes, bringing to life polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with outstanding properties. However, the synthesis of these Si-based inks is generally complex and expensive. Here, we prove that a polysilane ink, obtained as a byproduct of silicon gases and derivatives, can be used successfully for the synthesis of poly-Si by laser annealing, at room temperature, and for n- and p-channel TFTs. The devices, fabricated according to CMOS compatible processes at 350 °C, showed field effect mobilities up to 8 and 2 cm2/(V s) for n- and p-type TFTs, respectively. The presented method combines a low-cost coating technique with the usage of recycled material, opening a route to a convenient and sustainable production of large-area, flexible, and even disposable/single-use electronics.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

Separation of the Geometric Current in Charge Pumping Measurement of Polycrystalline Si Thin-Film Transistors

In the charge pumping (CP) measurement of polycrystalline Si (poly-Si) thin-film transistors (TFTs), an experimental approach is developed to evaluate and separate the geometric current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> ) from the measured CP current based on a group of TFTs with different channel widths and fixed channel length. Along with the separation of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> , a new method is proposed to reliably characterize the trap state density of TFTs. Without the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">geo</sub> , the overestimation in CP measurement is avoided even for short CP pulse transition times. Moreover, critical transition time for the occurrence of geometry effect is determined, which agrees well with the prediction from a physical model of diffusion controlled carrier evacuation.

Fabrication of high performance thin-film transistors via pressure-induced nucleation.

We report a method to improve the performance of polycrystalline Si (poly-Si) thin-film transistors (TFTs) via pressure-induced nucleation (PIN). During the PIN process, spatial variation in the local solidification temperature occurs because of a non-uniform pressure distribution during laser irradiation of the amorphous Si layer, which is capped with an SiO2 layer. This leads to a four-fold increase in the grain size of the poly-Si thin-films formed using the PIN process, compared with those formed using conventional excimer laser annealing. We find that thin films with optimal electrical properties can be achieved with a reduction in the number of laser irradiations from 20 to 6, as well as the preservation of the interface between the poly-Si and the SiO2 gate insulator. This interface preservation becomes possible to remove the cleaning process prior to gate insulator deposition, and we report devices with a field-effect mobility greater than 160 cm2/Vs.

A New Model for the 1/f Noise of Polycrystalline Silicon Thin-Film Transistors

An alternative model for the 1/f noise of polycrystalline Si thin-film transistors (poly-Si TFTs) is developed. The model adequately incorporates the grain boundary (GB) effect, different from previous work, however, the current noise is attributed to fluctuations in both carrier number and the GB barrier caused by carrier trapping/detrapping between the channel inversion carriers and the intragrain traps within the GB depletion region. The large dispersion of the trapping time constants in the 1/f noise behavior is attributed to the variation in carrier tunneling distance. The model fits the noise data very well in the low-drain current region. Based on the model, the effective density of states of the intragrain traps is obtained, providing a feasible method to evaluate the grain quality of poly-Si TFTs.

Suppress Dynamic Hot-Carrier Induced Degradation in Polycrystalline Si Thin-Film Transistors by Using a Substrate Terminal

Dynamic hot-carrier induced degradation is a major reliability issue for polycrystalline Si thin-film transistors (TFTs) under various pulsed voltage operations. To suppress the degradation, four-terminal TFT with an additional substrate terminal connected to the floating channel is proposed. The role of the substrate terminal is to supply majority carriers during the fast voltage transition and eliminate the nonequilibrium state associated with the channel/source and channel/drain junctions. It is demonstrated that device lifetime can be extended by more than one order of magnitude using the proposed structure. It can be more effective for forward biased substrate terminal and for narrow width TFTs, providing a feasible solution to enhance the TFT reliability.

A technique for local area transfer and simultaneous crystallization of amorphous silicon layer with midair cavity by irradiation with near-infrared semiconductor diode laser

A technique for local layer transfer and simultaneous crystallization of amorphous silicon (a-Si) films with midair cavity induced by near-infrared semiconductor diode laser (SDL) irradiation is demonstrated. After SDL irradiation, the silicon (Si) films were completely transferred and crystallized simultaneously on counter substrates. Electron backscatter diffraction pattern maps confirmed that the maximum grain size of the transferred Si films is 20 µm. High-performance polycrystalline Si thin-film transistors (TFTs) were successfully fabricated on the locally transferred Si films. These TFTs showed a high on/off ratio of more than 106 and a field-effect mobility as high as 492 cm2 V−1 s−1.

An Analytical Subthreshold Model of Polycrystalline Silicon Thin-Film Transistors Based on Meyer-Neldel Rule

It is demonstrated that the subthreshold region of polycrystalline Si thin-film transistors contains both the channel full inversion and channel partial inversion regimes. Channel inversion charge sheet density is modeled based on the gate-to-channel capacitance measurement. Following the observation of the Meyer-Neldel rule for effective channel mobility (μeff) in the subthreshold region, a μeff model is constructed with the physical origin of multiphonon excited carrier thermionic emission over the grain boundary (GB) barriers. Then, by considering the carrier drift, an analytical subthreshold drain current model is developed. Subsequently, an analytical expression for subthreshold swing (SS) is derived. The gate voltage (Vg) induced GB barrier lowering effect is determined to be the key mechanism for subthreshold behavior. Besides, the Vg point of channel full inversion is demonstrated to be a key point of the subthreshold region, where SS reaches a minimum.

Layer Transfer and Simultaneous Crystallization Technique for Amorphous Si Films with Midair Structure Induced by Near-Infrared Semiconductor Diode Laser Irradiation and Its Application to Thin-Film Transistor Fabrication

A novel layer transfer and simultaneous crystallization of amorphous silicon (a-Si) films induced by near-infrared semiconductor-diode-laser (SDL) irradiation has been investigated. The a-Si films supported by narrow quartz columns on a starting quartz substrate and a counter substrate [glass and poly(ethylene terephthalate)] were in face-to-face contact, and an SDL irradiated the a-Si films with midair structure. After SDL irradiation, the Si films were completely transferred and crystallized simultaneously on the counter substrates. In-situ monitoring revealed that the layer transfer took place either in the solid phase or the liquid phase followed by phase transformation in the cooling period. High performance polycrystalline Si thin-film transistors were successfully fabricated on the transferred Si films, which showed a high on/off ratio of more than 105 and a field-effect mobility as high as 268 cm2 V-1 s-1.

High performance low temperature polycrystalline Si thin-film transistors fabricated by silicide seed-induced lateral crystallization

A novel and simple crystallization method for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using Ni silicide seed-induced lateral crystallization (SILC) was proposed in this study, and it includes no additional deposition and/or etching processes that are not found in the fabrication of conventional metal-induced lateral crystallization (MILC) TFTs. The poly-Si thin films crystallized by SILC were characterized by x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and Micro-Raman spectroscopy. The electrical properties were obtained from ID-VG transfer curves and the interface trap density was determined by Levinson plot analysis. The results show that SILC poly-Si films have lower Ni contamination, better crystallinity, and higher crystalline fraction than MILC poly-Si films. The p-channel SILC poly-Si TFTs exhibited a mobility of 66 cm2/V·s, a minimum leakage current of 3.4 × 10−11 A at VD = −5 V, a subthreshold slope of 0.85 V/dec, and a maximum on/off ratio of 5.0 × 106, all of which resulted in a high-performance device which surpassed conventional MILC poly-Si TFTs.

Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors

In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility μFE, rising from 14.33 to 22.33 cm2/ V.s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility _FE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified.

Formation of n-channel polycrystalline-Si thin-film transistors by dual source/drain implantation

Formation of n-channel poly-Si TFT devices by the dual source/drain (S/D) implantation scheme has been studied. By the dual-implantation scheme that performs both the high-energy/low-dose large-angle-tilt-implantation and the n +-S/D implantation in the same mask layer, lightly doped n −-region can be effectively formed without needing extra process steps and photo-mask layer in CMOS process integration. As a result, the off-state leakage current of the resultant TFT devices is significantly improved to be about two orders smaller than that for the conventional samples that just receives single n +-S/D implantation, attributable to lower electric field intensity near the drain region. However, by the dual-implantation scheme that employs high-energy/low-dose implantation with no tilt angle, namely as a conventional double-diffused drain scheme, the resultant device characteristics are just comparable to those caused by the conventional scheme.

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.

Effects of independent double-gated configuration on polycrystalline-Si nonvolatile memory devices

A polycrystalline-Si thin-film transistor configured with independent double-gated structure and ultrathin channel film is proposed for use as a Si-oxide-nitride-oxide-Si memory device. Taking advantage of additional control gate bias offered by the independent double-gated scheme in addition to the driving gate, this work demonstrated that the reading window and programming efficiency can be improved by applying a proper control gate bias. It is also found that the relationship between programming/erasing speed and control gate bias is strongly related to channel film thickness. Our results indicate that the independent double-gated device possesses promising potential for future nonvolatile memory applications.

Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation

Excellent n-channel poly-Si thin-film transistors (poly-Si TFTs) have been formed by using retrograde channel scheme with channel doping implantation and extra counter-doping implantation. As compared to the conventional sample with undoped channel layer, a much smaller leakage current can be achieved by boron-doping the poly-Si channel layer, due to a significantly reduced depletion region. However, the on-state characteristics are degraded. A retrograde channel scheme, implemented by further phosphorus counter-doping the surface of the boron-doped channel layer, is proposed for lowering the channel surface doping concentration without changing the bulk channel doping concentration. By using the retrograde channel scheme, an off-state leakage current as low as that for the normal channel-doping scheme may be achieved, while yielding excellent on-state I– V transfer characteristics.