Point DCT Research Articles

CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation

—In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power-of-two point DCT, and develop its corresponding efficient VLSI implementation. The proposed algorithm has some distinguish advantages, such as regular Cooley-Tukey FFT-like data flow, identical post-scaling factor, and arithmetic-sequence rotation angles. By using the trigonometric formula, the number of the CORDIC types is reduced dramatically. This leads to an efficient method for overcoming the problem that lack synchronization among the various rotation angles CORDICs. By fully reusing the uniform processing cell (PE), for 8-point DCT, only four carry save adders (CSAs)-based PEs with two different types are required. Compared with other known architectures, the proposed 8-point DCT architecture has higher modularity, lower hardware complexity, higher throughput and better synchronization.

CORDIC Based Fast Algorithm for Power of Two Point DCT

In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power of two point DCT. The proposed algorithm has some distinguish advantages, such as regular data flow like the Cooley-Tukey FFT, identical post-scaling factor, and the rotation angles of the CORDICs in DCT are arithmetic sequence. By using the sum formula and double angle formula, we dramatically reduce the CORDIC types in the proposed algorithm. For the purpose of gain fast speed, we use Carry Save Adder (CSA) as the basic cell of each part and Carry Look-ahead Adder (CLA) to produce the outputs in the final level. Compared with other known architectures, the proposed 2-point DCT architecture has lower hardware complexity, higher throughput and better synchronization

A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design

SUMMARY This paper describes a unified VLSI architecture which can be applied to various types of transforms used in MPEG-2/4, H.264, VC-1, AVS and the emerging new video coding standard named HEVC (High Efficiency Video Coding). A novel design named configurable butterfly array (CBA) is also proposed to support both the forward transform and the inverse transform in this unified architecture. Hadamard transform or 4/8-point DCT/IDCT are used in traditional video coding standards while 16/32-point DCT/IDCT are newly introduced in HEVC. The proposed architecture can support all these transform types in a unified architecture. Two levels (architecture level and block level) of hardware sharing are adopted in this design. In the architecture level, the forward transform can share the hardware resource with the inverse transform. In the block level, the hardware for smaller size transform can be recursively reused by larger size transform. The multiplications of 4 or 8-point transform are implemented with Multiplierless MCM (Multiple Constant Multiplication). In order to reduce the hardware overhead, the multiplications of 16/32 point DCT are implemented with ICM (input-muxed constant multipliers) instead of MCM or regular multipliers. The proposed design is 51% more area efficient than previous work. To the author’s knowledge, this is the first published work to support both forward and inverse 4/8/16/32-point

N Point DCT VLSI Architecture for Emerging HEVC Standard

This work presents a flexible VLSI architecture to compute the N‐point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 32 × 32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real‐time processing of 1080P HD video codec running at 150 MHz.

Mixed-radix discrete cosine transform

Presents two new fast discrete cosine transform computation algorithms: a radix-3 and a radix-6 algorithm. These two new algorithms are superior to the conventional radix-3 algorithm as they (i) require less computational complexity in terms of the number of multiplications per point, (ii) provide a wider choice of the sequence length for which the DCT can be realized and, (iii) support the prime factor-decomposed computation algorithm to realize the 2/sup m/3/sup n/-point DCT. Furthermore, a mixed-radix algorithm is also proposed such that an optimal performance can be achieved by applying the proposed radix-3 and radix-6 and the well-developed radix-2 decomposition techniques in a proper sequence.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>