PNP BJT Research Articles

Pyro Squib Circuit Design with Stable Constant Current Driving Method

We proposed a design method for constant current pyro squib circuit. The current method using N MOSFET for the stability problem has a weakness of the current change, requiring a new design. This paper identified the problem with conventional squib circuit where the current is reduced by 25 % when maximum resistance is 3 ohms. Thus, we proposed a stable constant current driving circuit using P MOSFET and PNP BJT. We confirmed stable constant circuit operation through simulations and measurements of the proposed circuit design where the current did not change until the resistance reached 3 ohms.

A Charge Balancing 1450 um2 PNP-Based Thermal Sensor for Dense Thermal Monitoring

Thermal sensors are used in CPU’s to detect hot spots and determine voltage levels. Since thermal gradients can be instruction dependent, there can be as many as 40 sensors/chip, which requires them to be compact. The industry standard for thermal sensors is the bandgap based PNP BJT sensor, because of its predictable and well-known physics. In this brief, a 1450 $\mu {\mathrm{ m}}^{2}$ charge-sharing BJT-based thermal sensor, with a 50 $\mu {\mathrm{ m}}^{2}$ sensing element, in 65nm is described. After a 1-point trim, the sensor exhibits a peak-to-peak accuracy of −2/+4°C over a 150°C range. After a 2-point trim, this becomes −2.5/+1.5°C over the same range. It also achieves a resolution of 0.22°C in an $821~\mu \text{s}$ conversion time. These specifications, as well as the small area, make the sensor attractive for dense CPU thermal monitoring.

Analytical model for total ionizing dose-induced excess base current in PNP BJTs

This work analytically models the crucial physical mechanisms accountable for the defect kinetics and the degradation of base current in PNP BJTs. Both the space charge and bimolecular mechanisms have been incorporated to elicit the defect dynamics (oxide charge and interface trap) following ionization radiation. Thereafter, two novel insights into the ionization damage on SiO2 of bipolar structure are provided, which includes the coupled effect of the two defect mechanisms and the existence of an “additional” hydrogen sensitivity in the bimolecular mechanism. A previous device model has been updated to describe the response of base current degradation to defects build-up. Further, a closed-form compact expression for the excess base current is provided, which is an explicit function of the total ionizing dose, dose rate, and hydrogen concentration. The new model closely fits the experimental data from several devices, including RF25 capacitor, gate controlled lateral PNP BJT, and LM124 amplifier. Our model delivers a practical approach to deduct the oxide charge modulation effect on excess base current. Thereafter, the relation between the modified excess base current and total ionizing dose is linear. Furthermore, this work suggests a practical approach, called as “offset current approach”, to predict the excess base in PNP BJTs at low dose rate.

A 0.5-V Supply, 36 nW Bandgap Reference With 42 ppm/°C Average Temperature Coefficient Within −40 °C to 120 °C

This paper presents a switched capacitor network (SCN)-based bandgap voltage reference (BGR) circuit designed and implemented in a 65nm standard CMOS process with a wide temperature range, high precision, low supply voltage and low power consumption for IoT device application. The proposed BGR employs a 2x charge pump with ripple optimization design to supply the ${V} _{\mathbf {EB}}$ generator, which can relax ${V} _{\mathbf {DD}}$ from 0.9V to 0.5V.A proportional to absolute temperature (PTAT) current source is proposed to bias the PNP BJT in order to reduce the nonlinearity of ${V} _{\mathbf {EB}}$ . Moreover, a voltage divider SCN with low leakage consideration to form the complementary to absolute temperature (CTAT) voltage is designed to reduce the nonlinearity of its coefficient, while a series-parallel SCN with adjusted clock swing to form the PTAT voltage is designed to improve the line regulation of the BGR. The measurement result shows that the proposed BGR has a temperature coefficient (TC) of 42 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.2mV/V or 0.64%/V from 0.5V to 1V. Based on 6-chip test result, it shows a $3\sigma / \mu $ variation of 3.08% before trimming, while 0.36% after trimming.

A High Performance Current-Mode Instrumentation Amplifier with Level Shifter for Single Power Biomedical Applications

In this paper, a high performance current-mode instrumentation amplifier has been proposed with low noise, low power and high CMRR features. The proposed design can adjust the gain with an external resistor for the processing of various biomedical signals. To reduce the noise of the amplifier, two design methods including PMOS input and lateral pnp BJT input have been implemented to improve the prior arts. To meet the single power supply need, a biomedical voltage level shifter is also proposed for low cost CMOS implementation. Based on the post-layout simulation results, the presented current-mode amplifier achieves high CMRR over 120 dB, power consumption of 61 uW at 1.8-V supply using standard 0.18-um CMOS technology.

Novel PNP BJT Structure to Improve Matching Characteristics for Analog and Mixed Signal Integrated Circuit Applications

Novel PNP BJT Structure to Improve Matching Characteristics for Analog and Mixed Signal Integrated Circuit Applications

Improved Manufacturability of AlGaAs/GaAs Pnp Heterojunction Bipolar Transistors

Specially designed Pnp heterojunction bipolar transistors (HBT's) in the AlGaAs/GaAs material system can offer improved radiation response over commercially-available silicon bipolar junction transistors (BJT's). To be a viable alternative to the silicon Pnp BJT, improvements to the manufacturability of the HBT were required. Utilization of a Pd/Ge/Au non-spiking ohmic contact to the base and implementation of a PECVD silicon nitride hard mask for wet etch control were the primary developments that led to a more reliable fabrication process. The implementation of the silicon nitride hard mask and the subsequent process improvements increased the average electrical yield from 43% to 90%.

A CMOS bandgap reference voltage generator with reduced voltage variation and BJT area

This paper proposes a new bandgap reference (BGR) circuit which adopts a cascode current mirror biasing for reducing the reference voltage variation and a novel sizing method for reducing the PNP BJT area. The proposed BGR was designed and fabricated using 0.18 μm triple-well CMOS process which provides only normal V TH transistors. The reference voltage variation of BGR was reduced from 0.5 mV (conventional) to 0.09 mV (proposed) using cascode current mirror biasing method. And the ratio of BJT emitter areas was reduced by a factor of 20 through the novel sizing method.

A CMOS Bandgap Reference Voltage Generator for a CMOS Active Pixel Sensor Imager

This paper proposes a new bandgap reference (BGR) circuit which takes advantage of a cascode current mirror biasing to reduce the V<TEX>$\_$</TEX>ref/ variation, and sizing technique, which utilizes two related ratio numbers k and N, to reduce the PNP BJT area. The proposed BGR is designed and fabricated on a test chip with a goal to provide a reference voltage to the 10 bit A/D(4-4-4 pipeline architecture) converter of the CMOS Active Pixel Sensor (APS) imager to be used in X-ray imaging. The basic temperature variation effect on V<TEX>$\_$</TEX>ref/ of the BGR has a maximum delta of 6 mV over the temperature range of 25<TEX>$^{\circ}C$</TEX> to 70<TEX>$^{\circ}C$</TEX>. To verify that the proposed BGR has radiation hardness for the X-ray imaging application, total ionization dose (TID) effect under Co-60 exposure conditions has been evaluated. The measured V<TEX>$\_$</TEX>ref/ variation under the radiation condition has a maximum delta of 33 mV over the range of 0 krad to 100 krad. For the given voltage, temperature, and radiation, the BGR has been satisfied well within the requirement of the target 10 bit A/D converter.

Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2/spl times/10/sup 12//cm/sup 2/ at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4/spl times/10/sup 10//cm/sup 2/ in the buried oxide.

Gate-controlled lateral PNP BJT: characteristics, modeling and circuit applications

This paper describes the electrical characteristics, modeling and some circuit applications of a gate-controlled lateral pnp transistor (GC-LPNP) which has four electrodes-collector (C), base (B), emitter (E) and gate (G), and was fabricated using a 0.8 /spl mu/m BiCMOS technology. This device is composed of a surface PMOS FET and a bulk lateral pnp BJT in parallel, and it has unique dc characteristics of either variable current gain /spl beta//sub F/ of 10/sup 2//spl sim/10/sup 4/ for V/sub G/ variations from 0.4 to -0.4 V at V/sub E/ biases of 0.4 to 0.6 V, or variable transconductance g/sub M/ that increases by 3/spl sim/10 times as V/sub E/ increases from 0.4 to 0.7 V at V/sub G/ biases of -0.2 to -0.4 V. A circuit model of this new device, which is suitable for SPICE circuit simulation is proposed, and this model gives good agreement to the measured current-voltage curves over a wide range of V/sub C/-, V/sub E/- and V/sub G/-variations. Using this new four-electrode hybrid device, some special functional analog circuits, such as a variable-gain amplifier (VGA) and a mixer circuit, can be built very easily and exhibit good performance, For the VGA circuit, variations of the ac gain control of 0.4/spl sim/5.5 times for /spl delta/V/sub G/ varies over 1 V was obtained; and for the mixer, a conversion gain of 5 dB to 12 dB for input RF signal up to 400 MHz was obtained. PSPICE simulation results for the VGA circuit using the GC-LPNP device model are in good agreement with measurements. Finally, this new device which was fabricated using a typical BiCMOS technology, can be directly integrated with other digital/analog VLSI circuits for very attractive system applications, such as portable wireless communication systems.