P-n Diodes Research Articles

Porous silicon diodes operated near the electroluminescence threshold

Transient behavior and the onset voltage of the electroluminescence (EL) has been measured for a porous silicon light-emitting diode (PSi LED). Diodes were fabricated by anodization of the pn diode structure with contacts realized by deposition of gold pads. Higher onset voltages of the EL have been found for samples with shorter peak wavelengths. This is attributed to higher injection barriers for those samples, in agreement with a smaller expected average crystallite size. A red-shift of the EL is observed at the voltages near the EL threshold and an EL mechanism based on exciton generation is suggested. © 1997 Elsevier Science S.A.

GaN PN-Structures Grown by Hydride Vapor Phase Epitaxy

AbstractFor the first time, GaN pn-junctions were fabricated by hydride vapor phase epitaxy. GaN pn-structures were grown directly on 6H-SiC substrates without any buffer layer. Undoped GaN layers were n-type with Nd-Naconcentration ranged from 1×1017to 5×1018cm−3. Magnesium was used as an acceptor to grow p-type GaN layers. Mg atomic concentration determined by secondary ion mass spectroscopy ranged from 5×1019to 5×1020cm−3. As-grown GaN layers doped with Mg were p-type, and p-type conductivity was improved by post-growth anneal. Mesa diodes with a vertical current flow geometry were formed by reactive ion etching. The position of the GaN pn-junction was determined by the electron beam induced current method. The electrical characteristics of the pn diodes were studied. Electroluminescence from the pn diodes was measured.

Characterization of a porous silicon diode with efficient and tunable electroluminescence

Electrical and optical properties of electroluminescent porous silicon pn diodes have been investigated. The measurements were performed under pulsed conditions to maintain high quantum efficiency (∼0.2%) operation. Diodes with different peak wavelengths, obtained by varying the etching parameters, were used. A high correlation between electroluminescence (EL) and photoluminescence (PL) of porous silicon (PSi) structures was observed: similar luminescence peak position, spectral width, quantum efficiencies, decay time constants, and luminescence quenching at increasing temperature, suggesting the same recombination mechanism for both EL and PL. The temperature dependence of the forward current and EL revealed a thermally activated conduction mechanism with an activation energy of ∼0.1–0.2 eV which is attributed to potential barriers in the undulating silicon wires. EL quenching and a redshift of the EL peak at an increased temperature were also observed. This is attributed to shorter nonradiative lifetimes and a thermally enhanced escaping of carriers from ‘‘active’’ crystallites. Finally, exhausting of the EL during long pulse durations has been characterized and we propose a charging mechanism in the PSi network as a possible origin.

A solid‐phase epitaxy with clean surface formation using SiH4 and Evaluation of SOI Layer

AbstractWe investigated a method of solid‐phase epitaxy (SPE) using low‐vacuum, low‐pressure chemical vapor deposition (LPCVD) equipment without the load lock chamber that is usually used for the Si LSI process. This is a new method of clean surface formation in which the Si substrate is heated after seed formation in an atmosphere of SiH4 gas. Using this method, an L‐SPE length of 4 μm was obtained. The reason for the success of this method appears to be that the seed surface cleaned by HF dipping is preserved by the SiH4 gas.To evaluate the quality of the silicon‐on‐insulator (SOI) layer formed by this method, a MOSFET and a PN diode were experimentally produced. The MOSFET exhibited normal transistor action, which confirmed that the SOI layer had satisfactory quality without any problem in manufacturing the MOSFET. However, it was found that the n value of the forward direction current characteristic of the PN diode was 1.156 and that the SOI layer had more recombination centers than the Si substrate (n = 1.050).

A sensitive technique for detecting low concentrations of deep level traps: Current-source deep level transient spectroscopy

A defect characterization method is presented that promises to provide improved defect detection sensitivity. The new technique involves the use of current-source biasing of a pn diode. Under current-source bias the junction voltage is transient, whereas standard deep level transient spectroscopy typically involves voltage-source bias with either capacitance or current transients. Computer simulations predict voltage transients of 5 mV from samples that, under identical trap capture and emission conditions, yield capacitance and current transients of only 0.2 fF and 0.7 pA. The new approach can tolerate large leakage currents, and the voltage transient amplitude is independent of device area.

Temperature dependent electrically detected magnetic resonance studies on silicon pn diodes

We report on electrically detected magnetic resonance (EDMR) studies in silicon pn diodes in the temperature range from 30 to 300 K. In the range from 150 to 300 K the resonance effect is, as usually observed, much larger than expected by spin polarization. From 150 K down to 30 K the spin resonance effect increases by a factor of 25, which is attributed to spin polarization of free electrons and electrons bound to recombination centers. Our investigation suggests that at least two different mechanisms contribute to the EDMR signal.

The numerical solution of Poisson's equation in a pn diode using a spreadsheet

The numerical calculation of the potential distribution in a pn diode is presented using a spreadsheet. It can be included in an introductory course in semiconductor device physics as a demonstration of the numerical analysis of devices. It is also a demonstration of the numerical solution of Poisson's equation when the charge density is a function of the potential, and is appropriate for a section on numerical methods in an introductory course in electromagnetics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pn junctions in mixed ionic-electronic conductors induced by chemical and electrical potential gradients

Non uniform charged defect distribution can arise in single phase, a priori uniform, mixed ionic-electronic conductors (MIECs) subject to gradients in the chemical potential and/or to applied voltages. The electronic defects may form graded n, graded p regions and pn or pin junctions. Yet this need not require the existence of a space charge. In the case of zero space charge the I − K characteristics of the pn junctions are very different from those of normal pn diodes. The electronic defect distribution for the main types of MIECs are discussed and the effect of chemical potential gradient and applied voltage in the steady state are demonstrated. Criteria for neglecting the space charge are given.

Electric Breakdown in Nitride PN Junctions

ABSTRACTElectric breakdown of mesa terminated GaN and AlGaN pn diodes was investigated. The nitride pn structures were grown on 6H-SiC (0001) wafers by metalorganic chemical vapor deposition (MOCVD). Mesa structures were fabricated by reactive ion etching (RIE). Capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the pn junctions were measured. It was found that the junctions were linearly graded. Microplasmic breakdown was observed. The breakdown voltage for GaN and AlGaN diodes ranged from 40 to 150 V and from 40 to 100 V, respectively. The electric breakdown field and temperature coefficient of the breakdown voltage were measured.

Characterization of proton interactions in electronic components

The responses of several np and pn diodes to 30, 100, 200 MeV protons were experimentally characterized. The results are compared with calculations using the HETC code. Well matching proton-induced SEU cross-sections are deduced.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A compact line and edge orientation detection sensor

A new line and edge orientation detection sensor using four position-sensitive devices is presented. This sensor is composed of four oblong position-sensing devices configured in a rectangular fashion. Each device detects the center of gravity of a light stripe on the device. By combining these positions obtained from four devices, a line orientation can be calculated. The simulation result demonstrates the translation invariance as well as the linewidth invariance if the sensor dimension is chosen such that the width/length ratio is smaller than or equal to 0.1. A pn diode formed by the n-well and the p-substrate shows the best position-sensing capability among the structures tested due to its relatively high well resistance. The position-sensing capability is investigated with different biases and under different levels of background illumination. Two position-sensing devices are used to measure the line orientation, which agrees well with the actual orientation.

Lateral polysilicon pn diodes: current-voltage characteristics simulation between 200 K and 400 K using a numerical approach

The current-voltage characteristics of lateral pn diodes fabricated in polysilicon layer grown by LPCVD on oxidized silicon substrates are analyzed versus temperature. The simulation proposed by Greve (1985) using the analytical current modeling is applied to forward and reverse junction currents for various temperatures; this modeling shows its limitations. Then to fit the experimental characteristics at low and high temperatures as well as at low and high current levels, a numerical modeling is developed taking into account the local electrical field effect on recombination and generation mechanisms at grain boundaries in the whole of the structure, i.e., quasi-neutral and depleted regions. This modeling allows one to fit the complete I-V experimental curves in the whole of the considered temperature range (200 K-400 K) with physical acceptable parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

UV-sensitive photodetectors based on metal-semiconductor contacts on 6H-SiC

Schottky diodes on Silicon Carbide (SiC) are of interest for many applications because of the relatively simple fabrication process compared to pn diodes. In this work we have fabricated Schottky diodes by evaporation of Ti on n-type an p-type 6H-SiC. Most of the diodes show good rectifying behaviour with very low reverse current and an ideality factor below 1.20. The photo response of the diodes has been measured in the range 200-400 nm. The peak sensitivity varies in the range 250-300 nm depending mainly on substrate doping.

Tem Observation of the Damages in Heavily Ion-Implanted Fine Si Columns

AbstractSi nanometer structures are promising for exhibiting the quantum size effect at temperatures even as high as a room temperature. The present work investigates by TEM the damages induced by a heavy ion-implantation to the fine Si columns, aim of fabrication of 1-D tunneling PN diode in future. Si columns are fabricated by electron beam lithography and reactive ion etching, followed by thinning by thermal oxidation of Si . Ultra fine Si column with a diameter of 8 nm are successfully formed. TEM lattice image observations for fine Si columns, which are subject to ion-implantation and subsequent annealing, are carried out. In the case of heavy doping of As, as well as BF2, as-doped structure is amorphous, and recrystallization is observed after annealing at 1000 °C for 30 min. Typical damages such as dislocations which are parallel to the {111} planes and Si micro-crystals which are differently oriented from the Si single crystal substrate are observed for Si columns with diameters larger than 40nm. However, it should be noted that no damage is observed for fine Si columns with diameters less than 20nm. It is suggested that defects are diffused out to the surface or the Si/SiO2 interface for ultra fine Si columns during annealing.

Reduction of Leakage Current and Minority Carrier Lifetime in Platinum-Diffused pn Diodes

We propose a novel method to control the depth profiles of platinum-related trap concentration in platinum-diffused silicon p+n diodes and to improve their electrical properties, leakage current and lifetime. Platinum has been introduced into silicon wafers and p+n diodes by one- or two-step heat treatment. The experimental results show that we can simultaneously minimize the leakage current and minority carrier lifetime, especially by the two-step heat treatment. This is the first proposal to overcome the trade-off relationship between the leakage current and lifetime. The experiment also proves that the dominant level for both the leakage current and minority carrier lifetime is a level at Ec-0.52 eV.

Simulation of capacitance-voltage profiles for the analysis of measurements at a p-type Si-SiGe-Si single quantum well

Simulations of apparent doping profiles as obtained from C-V measurements at pn or Schottky diodes are used to analyse data measured at a Si-SiGe-Si single quantum well device. C-V characteristics are simulated by numerically solving Poisson's equation for a multilayer structure using the algorithm of Rimmer, Missous and Peaker (1991). Some refinements are given to improve the precision and stability of this method. The valence band offset for a SiGe layer (4% Ge content) on a Si substrate is deduced from temperature-dependent C-V measurements to be Delta E=25-30 meV. The main accuracy-limiting factor for a band offset determination from C-V measurements is the influence of doping inhomogeneities, but the error can be reduced by taking into account C-V profiles measured at different temperatures.

Visible light emission from heavily doped porous silicon homojunction pn diodes

We observed visible light emission with a peak wavelength of 640 nm from forward biased, heavily doped porous silicon homojunction pn diodes. The light emission is attributed to electron-hole recombination across the direct band gap of the monocrystalline quantum wires which make up the porous silicon junction layers.

High voltage 6H-SiC rectifiers: prospects and progress

Summary form only given. There are several crucial device fabrication issues that must be solved before truly advantageous SiC power devices can be realized experimentally. Progress in the fabrication of experimental high-voltage epitaxial pn and Schottky junction 6H-SiC diodes is reported. Doping concentrations in 6H-SiC epilayers grown by atmospheric-pressure chemical vapor deposition have been reduced, making possible the fabrication of 2000-V silicon carbide diode rectifiers ever reported. A 24- mu m-thick 2*10/sup 15/ cm/sup -3/ n-type epilayer was the key to the 600-V improvement in reported 6H-SiC blocking voltage in the p/sup +/n mesa-structure diodes. The devices on this wafer were small enough (areas >

Temperature measurement by means of semiconductor diode in pulse mode

In case of temperature measurement utilizing forward-biased pn junction, a polarization current is necessary because it is what indicates the pn diode into an operating mode. Simultaneously, with the diode into the operating mode, the polarization current heats the pn junction and impedes measurement. The usual solution to this problem is to reduce the current through the diode. If the current is passed through the diode only at the moment of measurement and for a single brief impulse, the average current, as well as the amount of heat given off to the pn junction, is drastically reduced. The described pulsed-diode thermometer has an average relative error (within 20–100 °C range) of ΔT/T=0.25%.

Self-Scanning Light-Emitting Device (SLED) Using pnpn Thyristor Structure

We propose and demonstrate a new functional optoelectronic device, the “self-scanning light-emitting device (SLED).” The SLED consists of light-emitting thyristors whose turn-on voltages interact with each other through the resistor network. The SLED acts as an optical shift register, and the light-emitting element is automatically transferred by input clock pulses. We successfully demonstrated GaAs SLED operation using three-phase transfer clock pulses, and obtained 3 MHz as the maximum transfer rate. Moreover, we propose here the diode-coupled SLED, where the turn-on voltages of the thyristors interact through the pn diode in order to obtain the transfer operation driven by a two-phase clock pulse. The SLED has several unique functions and will become a new key device in the optoelectronic field and in optical information processing.