Platform For Real-time Applications Research Articles

Framework for Automated Earthquake Event Detection Based on Denoising by Adaptive Filter

Automated detection of the P-wave arrival for real-time earthquake-early-warning-system employing conventional short-time-average/long-time-average (STA/LTA) algorithm is prone to suffer from erroneous detection due to high background noise. This paper introduces an enhanced variable step-size least mean square (EVSSLMS) algorithm for considerably improving the P-wave detection. The proposed event detection scheme employs the EVSSLMS algorithm for de-noising the seismic data followed by conventional STA/LTA algorithm to detect arrival of the P-wave. The EVSSLMS algorithm outperforms the existing trigonometric least mean square (TLMS), variable step-size LMS (VSSLMS), least mean logarithmic square (LMLS) and variable α-LMLS algorithms in terms of convergence speed and steady-state error and achieves a significant enhancement in detection accuracy by 42%, 33%, 25% and 23% at low signal-to-noise ratio (SNR) as compared to the existing TLMS, VSSLMS, LMLS, and variable-α LMLS algorithms, respectively. Moreover, a high-speed and low-complexity very-large-scale-integrated (VLSI) architecture has been implemented on both field-programmable-gate array (FPGA) and application-specific-integrated circuit (ASIC) platforms for realtime applications. Comparison of architectural performance of the proposed scheme with that of architecture designed to realize variable-α LMLS algorithm exhibits 36% less slice-delay-product whereas, its ASIC implementation exhibits 7.27% less areadelay-product, 9.31% less energy-per-sample with 5.2% more maximum achievable frequency.

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

High Speed computing meets ever increasing real-time computational demands through the leveraging of flexibility and parallelism. The flexibility is achieved when computing platform designed with heterogeneous resources to support multifarious tasks of an application where as task scheduling brings parallel processing. The efficient task scheduling is critical to obtain optimized performance in heterogeneous computing Systems (HCS). In this paper, we brought a review of various application scheduling models which provide parallelism for homogeneous and heterogeneous computing systems. In this paper, we made a review of various scheduling methodologies targeted to high speed computing systems and also prepared summary chart. The comparative study of scheduling methodologies for high speed computing systems has been carried out based on the attributes of platform & application as well. The attributes are execution time, nature of task, task handling capability, type of host & computing platform. Finally a summary chart has been prepared and it demonstrates that the need of developing scheduling methodologies for Heterogeneous Reconfigurable Computing Systems (HRCS) which is an emerging high speed computing platform for real time applications.

Non-enzymatic glucose sensing on long and short diamond nanowire electrodes

In this paper the fabrication of micrometer long boron-doped diamond nanowire (L-BDD NWs) electrodes is reported. The diamond nanowires were obtained by a maskless reactive ion etching process with oxygen plasma using 15μm thick polycrystalline boron-doped diamond (BDD) films as starting material. The resulting nanowire interfaces showed enhanced electrochemical activity towards the direct electrochemical detection of glucose under strong basic (pH12) condition when compared to flat BDD and short nanowires (S-BDD NWs). The robust response of these nanostructures with a detection limit of 60μM and a linear range up to 8mM and the ease of formation make L-BDD NWs a promising platform for real time applications.

Clasificador no Lineal Basado en Redes Neuronales con Funciones de Base Radial para Implementación en Sistemas de Punto Fijo

Para implementar máquinas inteligentes, es común requerir de sistemas de clasificación que sean eficientes y realizables en plataformas con bajo nivel de procesamiento. En este trabajo se presenta un método de diseño para estimar los parámetros de un clasificador basado en redes neuronales con funciones de base radial para ser implementado en sistemas de procesamiento digital con punto fijo. En principio, usando métricas estadísticas se obtiene el número de centroides necesarios para llevar las clases a un espacio que las haga linealmente separables, posteriormente aplicando el algoritmo k-medias se estima la ubicación de los centroides. Se determina la distancia de los puntos de entrenamiento a cada centroide, y usando aproximación por mínimos cuadrados se calculan los pesos de la función de salida. De esta manera, se obtiene un clasificador con una complejidad computacional reducida que permita ser usado en sistemas con requerimientos de bajo nivel de procesamiento como los de tiempo real.