Plasma Etch-back Research Articles

Area-Selective Atmospheric-Pressure Spatial ALD of SiO2 Using Interleaved Back-Etch Steps Yielding Selectivity > 10 Nanometer

Area-selective atomic layer deposition (AS-ALD) has great potential in reducing cost by maskless device manufacturing of patterned layers. Still, in this new bottom-up approach the selectivities currently obtained for film growth on patterned growth areas vs. that on the non-growth areas are often very limited. Also the substrate throughput values for conventional low-pressure ALD is too low for industrial acceptance (1,2). In this work we present a process for AS-ALD of SiO2 using intermittent plasma etch-back steps to increase the selectivity above 10 nm film thickness (3). In addition, the deposition process itself is performed in a spatial ALD reactor at atmospheric pressure which allows for achieving high throughput (4). AS-ALD of SiO2 on a substrate with pre-patterned SiO2 and ZnO areas was demonstrated using a chemo-selective inhibitor that chemisorbs preferentially on the non-growth area (ZnO) while allowing the deposition of SiO2 on the growth area (SiO2). In order to maximize the process selectivity, a blanket fluorocarbon plasma etch-back step was interleaved after every 110 ALD cycles. This way, selective SiO2 deposition up to ~ 30 nm film thickness was demonstrated (Fig. 1). Furthermore, X-ray Photoelectron Spectroscopy was carried out to verify the selectivity of the process: no Si was detected (detection limit 0.3 at. %) on the non-growth area, demonstrating the high selectivity of the process. The process presented here combines selective inhibitor chemisorption, plasma-based spatial ALD with high deposition rates and plasma etch-back steps to correct for selectivity loss. This approach is compatible with roll-to-roll and sheet-to-sheet concepts and can therefore enable high-throughput AS-ALD on large-area and flexible substrates. ----------------------------------------------------------------------------------------------------------------------------------------------------------------

CMP-less ILD0 Planarization Technology for Gate-Last Process

As CMOS technology scales to 32nm node and beyond, ILD0 planarization is one of critical technologies in high-K metal gate-last process integration. In this paper, a novel sub-micron gate-last process featuring with CMP-less spin-on glass/silicon oxide (SOG/SiO2) etch-back method was demonstrated for low cost logic platform. The innovative approach of SOG two steps plasma etch-back with O2 treatment can be successfully used for ILD0 planarization of gate-last process. SEM results indicated that there was fairly little "dish effect" and step height close to zero on the 0.4µm gate-stack array and finally achieved a good planarization on the whole substrate.

Metal gate etch-back planarization technology

Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO2 interface trimming. The within-the-wafer ILD thickness non-uniformity can reach 4.19% with a wafer edge exclusion of 5 mm. SEM results indicated that there was little “disheffect" on the 0.4 μm gate-stack structure and finally achieved a good planarization profile on the whole substrate. The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.

Optical spectroscopy of GaN microcavities with thicknesses controlled using a plasma etchback

The effect of an etch-back step to control the cavity length within GaN-based microcavities formed between two dielectric Bragg mirrors was investigated using photoluminescence and reflectivity. The structures are fabricated using a combination of a laser lift-off technique to separate epitaxial III-N layers from their sapphire substrates and electron-beam evaporation to deposit silica/zirconia multilayer mirrors. The photoluminescence measurements reveal cavity modes from both etched and nonetched microcavities. Similar cavity finesses are measured for 2.0 and 0.8 μm GaN cavities fabricated from the same wafer, indicating that the etchback has had little effect on the microcavity quality. For InGaN quantum well samples the etchback is shown to allow controllable reduction of the cavity length. Two etch steps of 100 nm are demonstrated with an accuracy of approximately 5%. The etchback, achieved using inductively coupled plasma and wet chemical etching, allows removal of the low-quality GaN nucleation layer, control of the cavity length, and modification of the surface resulting from lift-off.

Plasma etch-back planarization coupled to chemical mechanical polishing for sub 0.18 μm shallow trench isolation technology

A new plasma etch-back planarization technique is presented with countermasking to preplanarize shallow trench isolation (STI) substrates before chemical mechanical polishing (CMP). A preplanarization step is necessary since CMP alone cannot provide effective planarization for sub 0.18 technology due to the dishing effect. The preplanarization step uses the principle of two layer planarization technique which consists of spin coating a first photoresist layer, using a countermask for the lithographic step, flowing and curing the resist blocks in STI topographies, spin coating a second photoresist layer to planarize the residual topography, and transferring the final flat surface into the substrate using conventional plasma etch back. In difference with previous techniques, we used a special mask with oversizing and exclusion of all STI critical dimensions smaller than 1.55 μm, the zones with the smaller STI dimensions being masked using a special narrow lines grid. Such a masking strategy avoids any misalignment problem, where the resized first photoresist blocks are reflowed in STI topographies, leading to an easy planarization by the second resist layer. Additionally, the lithographic step is a noncritical step using conventional i-line resist. Using appropriate planarization model and simulation, the first layer thickness can be adjusted to get an effectively planarized topography. The final surface is then transferred into the oxide substrate using the plasma etch-back technique. Various gas mixtures were tested using LAM 4520 plasma etching equipment. The (Ar/CF4/O2) gas mixture was observed to fulfill etch-back requirements with better performance. Equality of etch rate in resist and in oxide can be adjusted by the O2/CF4 gas ratio. A design of experiment was used to determine the optimum conditions of plasma transfer of the planarized profile into the substrate. Finally, the preplanarized wafer is polished by CMP, resulting in an effectively planarized topography with residual topography smaller than 50 nm. The technique is a noncritical lithographic technique scaleable for technologies below 0.18 μm.

Direct bonding of GaAs films on silicon circuits by epitaxial liftoff

Epitaxial liftoff has emerged as a viable technique to integrate GaAs with silicon. The technique relies on the separation of a thin epi-GaAs film from its substrate followed by direct bonding of the thin film to a silicon substrate. The silicon substrate has to meet certain planarity and smoothness conditions in order to obtain high quality bonding. Unfortunately, processed silicon IC chips do not satisfy these conditions. In this paper, we report on the results of two different planarization techniques, plasma etch back and chemical-mechanical polishing, to integrate GaAs LEDs with silicon circuits using epitaxial liftoff. 4 by 8 arrays of GaAs LEDs have been integrated with silicon driver circuits using plasma etch back. We also have lifted off areas as large as 500 mm 2 and bonded them on 5″ device wafers by chemical-mechanical polishing. This can be essential for mass production of optoelectronic devices based on epitaxial liftoff.

Reactor Characterization for an SiO2 Plasma Etchback Process with Response‐Surface Methodology: Effects of Interelectrode Spacing

The characteristics of plasmas which are used to etch composite layers of sacrificial photoresist and underlying have been examined with experimental design and modeled empirically by response‐surface methodology using a Lam Research Autoetch 480 single‐wafer system. The effects of variations of process gas flow rates for (150–200 sccm) and (0–50 sccm), reactor pressure (900–2000 mtorr), and interelectrode spacing (4–6 mm) on the etch rates of and photoresist were explored at fixed radio frequency power (500W at 13.56 MHz) at . Variation in spacing shows different effects for these two materials; whereas the etch rates generally increase with increasing spacing as the other parameters are varied, the photoresist etch rates exhibit more complex behavior. At the lower spacing of 4 mm, neither film has a measurable etch rate for low settings of the other variables. The etch rates are virtually constant with increasing flow rate for low, middle, and high settings of the other variables. At low settings of the other variables, the photoresist etch rates are zero over the range of flow rates but increase with increasing flow rates for middle and high settings of the other variables. At a spacing of 4 mm, the etch rates of both films are negligible over the range of flow rates and the range of reactor pressure. At larger spacings the etch rates of photoresist increase with increasing flow rate, while the etch rates of are similar for middle and high settings of the other variables over the range of flow rates. Process optimization using the empirical models to attain suitable etch rates for both films for planarization of a composite layer of photoresist and with high etch uniformity was achieved at 500W of RF power, 1450 mtorr, 150 sccm of , 0 sccm , and a spacing of 5.5 mm. Hence, for a plasma with this reactor adequate planarization is obtained without the use of . The addition of small concentrations of to a plasma resulted in increasingly higher etch rates for photoresist as the process progressed.