The invention of CMP by IBM in 1983 represents an inflection point in the evolution of semiconductors. It was a bold and risky idea to mechanically apply abrasives to the surface of a wafer, but this new process for restoring a wafer to a planar state was the key to continued areal scaling and increased device complexity. Initially applied to a simple application for filling trenches with insulator, the potential of this technique was evident. Through understanding of material properties and subsequent manipulation of slurry chemistry, CMP was applied to enable the more challenging and technically critical processes for Shallow Trench Isolation and Tungsten contacts. The late 1990’s saw the introduction of copper interconnects. IBM was first to market this technology which continues to support conductors down to lines widths on the order of 10 nanometers! The CMP process required for copper interconnects demanded a thorough understanding of the materials present and potential surface phenomena for exploitation. For this need, a new and complex mechanism for copper planarization was invented. Equally challenging was the need for a subsequent non-selective barrier removal step. For this a unique, self-balancing approach was also invented, borrowing some elements from previous STI technology. Device architecture has progressed from planar geometry to FINFETs to Gate All Around, or Nanosheet technology. This evolution has required increasingly more CMP process steps with a concurrent demand for increased process control. Gate height control for Nanosheeets is currently paramount for performance, affected by many CMP steps in the process flow. A typical requirement is less than 1nm added variability per CMP step! Looking forward, CMP continues to be tapped to enable technology evolution. Polish steps are becoming part of the patterning process to enable pitch splitting for upcoming nodes. A VTFET integration approach can enable further area scaling but presents integration challenges; CMP is being asked to enable “third color” schemes for the protection of NFET vs PFET devices which is necessary at various points in the in the VTFET process flow. Heterogeneous Integration is demanding nanometer control of topography across large contact pads and large lateral distances. Finally, extreme scaling is creating fundamental challenges for metal polish at the contact and interconnect levels. CMP tool architecture currently does not provide for control of ambient conditions at the wafer surface during wet transport and post CMP cleaning. Subsequently, unwanted metal dissolution is observed. New tool designs will be needed to control wafer surface conditions, and particularly oxygen exposure through all steps within the CMP tool. This talk is dedicated to the special session in honor of Professor S.V. Babu