Placement Perturbation Research Articles

A comparison of the effects of mediolateral surface and foot placement perturbations on balance control and response strategies during walking

BackgroundBalance perturbation studies during walking have improved our understanding of balance control in various destabilizing conditions. However, it is unknown to what extent balance recovery strategies can be generalized across different types of mediolateral balance perturbations. Research questionDo similar mediolateral perturbations (foot placement versus surface translation) have similar effects on balance control and corresponding balance response strategies? MethodsKinetic and kinematic data were previously collected during two separate studies, each with 15 young, healthy participants walking on an instrumented treadmill. In both studies, medial and lateral balance perturbations were applied at 80% of the gait cycle either by a treadmill surface translation or a pneumatic force applied to the swing foot. Differences in balance control (frontal plane whole body angular momentum) and balance response strategies (hip abduction moment, ankle inversion moment, center of pressure excursion and frontal plane trunk moment) between perturbed and unperturbed gait cycles were evaluated using statistical parametric mapping. ResultsBalance disruptions after foot placement perturbations were larger and sustained longer compared to surface translations. Changes in joint moment responses were also larger for the foot placement perturbations compared to the surface translation perturbations. Lateral hip, ankle, and trunk strategies were used to maintain balance after medial foot placement perturbations, while a trunk strategy was primarily used after surface translations. SignificanceSurface and foot placement perturbations influence balance control and corresponding response strategies differently. These results can help inform the development of perturbation-based balance training interventions aimed at reducing fall risk in clinical populations.

Individual muscle responses to mediolateral foot placement perturbations during walking

Walking requires active control of frontal plane balance through adjustments to mediolateral foot placement and ground reaction forces. Previous work on mediolateral balance perturbations and control of foot placement has often focused on the bilateral gluteus medius muscles. However, additional leg and trunk muscles can influence foot placement by transferring power to the foot and pelvis during swing. Thus, the purpose of this study was to determine individual muscle contributions to balance control following medial and lateral foot placement perturbations. Ten participants performed treadmill walking trials which included perturbations immediately before randomized heel strikes. Muscle contributions to foot placement, ground reaction forces, trunk power and frontal plane external moments during representative perturbed and unperturbed gait cycles were estimated using musculoskeletal modeling and simulation. Net muscle contributions to foot placement were 61 ± 50% more medial during the first recovery step following lateral perturbations and 28 ± 14% less medial in the second recovery step following medial perturbations. Following lateral perturbations, the swing gluteus medius performed 57 ± 50% more lateral work and the stance gluteus medius performed 61 ± 50% more medial work on the foot. Following medial perturbations, the erector spinae performed 39 ± 33% less lateral work on the foot. Changes in net muscle work on the foot were inconsistent with changes in step width, suggesting that changes in step width were not due to active muscle control but rather the mechanical effect of the perturbation. These outcomes provide a foundation for future studies analyzing balance control in populations at risk of falling.

Gait Optimization of a Quadruped Robot Using Evolutionary Computation

Evolutionary Computation (EC) has strengths in terms of computation for gait optimization. However, conventional evolutionary algorithms use typical gait parameters such as step length and swing height, which limit the trajectory deformation for optimization of the foot trajectory. Furthermore, the quantitative index of fitness convergence is insufficient. In this paper, we perform gait optimization of a quadruped robot using foot placement perturbation based on EC. The proposed algorithm has an atypical solution search range, which is generated by independent manipulation of each placement that forms the foot trajectory. A convergence index is also introduced to prevent premature cessation of learning. The conventional algorithm and the proposed algorithm are applied to a quadruped robot; walking performances are then compared by gait simulation. Although the two algorithms exhibit similar computation rates, the proposed algorithm shows better fitness and a wider search range. The evolutionary tendency of the walking trajectory is analyzed using the optimized results, and the findings provide insight into reliable leg trajectory design.

Hip recovery strategy used by below-knee amputees following mediolateral foot perturbations

Lower-limb amputees have a higher risk of falling compared to non-amputees. Proper regulation of whole-body angular momentum is necessary to prevent falls, particularly in the frontal plane where individuals are most unstable. However, the balance recovery mechanisms used by lower-limb amputees when recovering from a perturbation are not well-understood. This study sought to understand the balance recovery mechanisms used by lower-limb amputees in response to mediolateral foot perturbations by examining changes to frontal plane whole-body angular momentum and hip joint work. These metrics provide a quantitative measure of frontal plane dynamic balance and associated joint contributions required to maintain balance during gait. Nine amputees and 11 non-amputees participated in this study where an unexpected medial or lateral foot placement perturbation occurred immediately prior to heel strike on the residual, sound or non-amputee limbs. Lateral perturbations of all limbs resulted in a reduced range of whole-body angular momentum and increased positive frontal plane hip work in the first half of single limb support. Medial perturbations for all limbs resulted in increased range of whole-body angular momentum and decreased positive frontal plane hip work, also in the first half of single limb support. These results suggest that medial foot placement perturbations are particularly challenging and that hip strategies play an important role in balance recovery. Thus, rehabilitation interventions that focus on hip muscles that regulate mediolateral balance, particularly the hip abductors, and the use of prostheses with active ankle control, may reduce the risk of falls.

The Cat and Mouse in Split Manufacturing

Split manufacturing of integrated circuits eliminates vulnerabilities introduced by an untrusted foundry by manufacturing only a part of the target design at an untrusted high-end foundry and the remaining part at a trusted low-end foundry. Most researchers have focused on attack and defenses for hierarchical designs and/or use a relatively high-end trusted foundry, leading to high cost. We propose an attack and defense for split manufacturing for flattened designs. Our attack uses a network-flow model and outperforms previous attacks. We also develop two defense techniques using placement perturbation—one using physical design information and the other using logical information—while considering overhead. The effectiveness of our techniques is demonstrated on benchmark circuits.

Logic Design Partitioning for Stacked Power Domains

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which connects voltage domains in series, can effectively improve power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced currents between different domains across multiple operating scenarios. Furthermore, level shifter insertion, along with placement constraints imposed by power domain regions, can incur significant power and area penalties. To the best of our knowledge, no existing work performs subblock-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced cross-domain current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floor plan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves an excellent current balance across stacked domains with less than 10% discrepancy, which results in up to more than $2\times$ battery lifetime improvements.

Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography

Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of “bimodal” challenges for timing analysis and optimization. We assess the potential impact of bimodal CD distribution on timing analysis and guardbanding, and find that the traditional “unimodal” characterization and analysis framework may not be viable for DPL. We propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an integer linear programming-based maximization of “alternate” mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure “double patterning correctness” after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable engineering change order (ECO) impact. With a 45 nm library and open-source design testcases, our timing-aware recoloring and placement optimization together achieve up to 271 ps (respectively, 55.75 ns) reduction in worst (respectively, total) negative slack, and 70% (respectively, 72%) reduction in worst (respectively, total) negative slack variation, respectively.

Pattern Sensitive Placement Perturbation for Manufacturability

The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features on wafers. The quality and robustness of lithography directly depend on layout patterns. It becomes imperative to consider the manufacturability issue during layout design such that the burden of lithography process can be alleviated. In this paper, three algorithms, namely, cell flipping algorithm, single row optimization approach and multiple row optimization approach, are proposed to tune any existing cell placement to be lithography friendly. These algorithms are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between critical dimension (CD) variation reduction and wirelength increase. Using lithography simulations, our experimental results demonstrate that over 15% CD variation reduction can be obtained in post-OPC stage by the new approaches while only less than 1% additional wire is introduced.

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source-shallow trench isolation (STI)-has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We conduct process simulation of a 65-nm production STI technology to generate mobility and delay impact models for STI stress. We then utilize these models to perform STI-stress-aware delay analysis of critical paths using Simulation Program with Integrated Circuit Emphasis (SPICE). We present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation and active-layer fill insertion to improve complementary metal-oxide-semiconductor performance. We assess the proposed analysis and optimization on small designs implemented with a 65-nm production cell library and a standard synthesis place-and-route flow. Our stress-aware timing analysis improves the clock frequency by 4.68% to 6.31% over traditional worst case analysis, and our optimization improves clock frequency by 2.44% to 5.26%. The frequency improvement through exploitation of STI stress comes at practically zero cost in terms of design area and wire length.

Detailed Placement for Enhanced Control of Resist and Etch CDs

Subresolution assist feature (SRAF) and etch-dummy-insertion techniques have been absolutely essential for process-window enhancement and CD control in photo and etch processes. However, as focus levels change during lithography manufacturing, CDs at a given ldquolegalrdquo pitch can fail to achieve manufacturing tolerances. Placed standard-cell layouts may not have the ideal whitespace distribution to allow for an optimal assist-feature insertion. This paper first describes a novel dynamic-programming-based technique for Assist-Feature Correctness (AFCorr) in detailed placement of standard-cell designs. At the same time, etch-dummy features are used in the mask data preparation flow to reduce CD skew between resist and etch processes and to improve the printability of layouts. However, etch-dummy rules conflict with the SRAF insertion because each of the two techniques requires specific design rules. We further present a novel SRAF-aware etch-dummy-insertion method (SAEDM) which optimizes the etch-dummy insertion to make the layout more conducive to the assist-feature insertion after the etch-dummy features have been inserted. Since placement of cells can create forbidden-pitch violations of resist process and can increase etch skew, the placer must also generate etch-dummy-correct placement. This can be solved by Etch-dummy Correctness (EtchCorr), which is an intelligent whitespace management for etch-dummy-corrected placement, an extension of the AFCorr methodology. These methods for enhanced resist and etch CD controls are validated on industrial test cases with respect to wafer printability, database complexity, and device performance. For benchmark designs, we validate the four methodologies: 1) AFCorr; 2) SAEDM; 3) AFCorr SAEDM; and 4) AFCorr EtchCorr SAEDM. The AFCorr placement perturbation achieves a significant reduction in forbidden pitches between polysilicon shapes. Using 1) flow, forbidden-pitch count of photo process is reduced by 76%-100% for 130 nm and by 87%-100% for 90 nm. Our novel Corr design-perturbation technique, which combines the AFCorr and EtchCorr methods, facilitates additional SRAF and etch-dummy insertions and, thus, reduces the CD skew between the photo and etch processes. After Corr with SAEDM, edge-placement-error count is also reduced by 91%-100% in the resist CD and by 72%-98% in the etch CD. Our methods provide a substantial improvement in CD control with negligible timing, area, and CPU overhead. The advantages of such correctness methods are expected to increase in future technology nodes.

On controlling perturbation due to repeaters during quadratic placement

Recent studies have shown that scaling causes the number of repeaters to grow rapidly. The author demonstrates that this growth leads to massive placement perturbations that break the convergence of today's interleaved placement and repeater-insertion flows. The author then presents two new force models for repeaters targeted towards quadratic placement algorithms. Finally, experiments demonstrate the effectiveness of the repeater modeling technique in preserving placement convergence (often accompanied by wire-length improvement) at the 45- and 32-nm technology nodes

Fast placement approaches for FPGAs

Recent trends in FPGA development indicate a strong shift toward design reuse through the use of intellectual property (IP). This design shift has motivated the development of Frontier, a timing-driven FPGA placement system that uses design macroblocks in conjunction with a series of placement algorithms to achieve highly routable and high-performance layouts quickly. In the first stage of design placement, a macro-based floorplanner is used to quickly identify an initial layout based on intermacro connectivity. Next, FPGA routability and performance metrics are used to evaluate the quality of the initial placement. Finally, if the floorplan is determined to be insufficient from a routability or performance standpoint, a feedback-driven placement perturbation step is employed to achieve a lower cost placement. For a collection of large reconfigurable computing benchmark circuits our timing-driven placement system exhibits a 2.6× speedup in combined place and route time versus commercial FPGA CAD software with improved design performance for most designs. It is shown that floorplanning, placement evaluation, and backend optimization are all necessary to achieve high-performance placement solutions.