Pixel-parallel Architecture Research Articles

Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination

Graph cut has been a popular approach widely used to solve the minimum cut problem, which is prevalent in computer vision tasks, although not limited to this field. Push-relabel is considered as one of the promising algorithms of graph cut due to its good potential to be parallelized. However, existing implementations often not only fail to fully exploit the available parallelism but also fail to make full use of the application context to reduce redundant computations. Therefore, they are not competent for application scenarios with high resolution and real-time requirements. To address the issue, we propose three novel techniques to achieve an ultra-fast and efficient FPGA implementation of a push-relabel algorithm. First, we propose a ripple push technique that significantly parallelizes push operations so as to accelerate the push-relabel convergence process. Second, we propose an early-termination technique that effectively removes redundant computations of the push-relabel algorithm. We also theoretically prove the correctness of our early-termination technique. Third, we propose a highly parallelized search technique called flood irrigation search (FIS). It quickly judges early termination conditions based on a pixel parallel architecture. Our implementation focuses on performance-sensitive applications that divide large images into small graph tiles with a specific size. Compared to the state-of-the-art FPGA implementations of push-relabel algorithms, experimental results show that our method can at least achieve <inline-formula> <tex-math notation="LaTeX">$8.93\times $ </tex-math></inline-formula> improvement of execution time.

Real Time Hardware Software Co-SimulationEdge Map Accumulation Based FeatureExtraction

There are many applications like automotive vehicle control, video surveillance, remote gesture control etc. for which high speed image processing employing high frame rate image sensors provide details on motion which is useful for improving the speed and precision of the recognition. Therefore, the proposed system presents that the VLSI is capable for extracting motion features from moving images. The extraction of motion features from moving images is developed by using row parallel and pixel-parallel architectures. This system proposes a novel fast texture feature extraction method which takes advantage of the similarities between the neighbouring pixels to estimate texture values. Here, firstly by using FPGA and MATLAB edge detection and mapping take place.The feature extraction and the filtering process can be done through the MATLAB.

A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture

A very-large-scale integration capable of extracting motion features from moving images in real time has been developed employing row-parallel and pixel-parallel architectures based on the digital pixel sensor technology. Directional edge filtering of input images is carried out in row-parallel processing to minimize the chip real estate. To achieve a real-time response of the system, a fully pixel-parallel architecture has been explored in adaptive binarization of filtered images for essential feature extraction as well as in their temporal integration and derivative operations. As a result, self-speed-adaptive motion feature extraction has been established. The chip was designed and fabricated in a 65-nm CMOS technology and used to build an object detection system. Motion-sensitive target image localization was demonstrated as an illustrative example.

A PWM-Mode Pixel-Parallel Image-Processing Circuit Performing Directional State-Propagation and Its Application to Subjective Contour Generation

As an approach to constructing highly organized and intelligent image recognition systems mimicking the visual architecture in the human brain, we have designed an image processing circuit that performs a directional pixel-state propagation algorithm based on a pixel-parallel architecture using pulse-width modulation (PWM) signals. Directional pixel-state propagation can be used for subjective contour generation, which is a typical function of the visual system in the human brain to fill gaps in natural-image information. A PWM-mode circuit can provide more compact circuit configuration than digital circuits, and can achieve focal-plane analog processing by combining with image sensors without A/D converters. Such circuits are suitable for repetitive algorithms, which require offset-free arithmetic. The proof-of-concept LSI chip has been designed and fabricated using a 0.25 $$\upmu $$μm mixed-signal CMOS process. There are 35 $$\times $$A— 35 processing units included in the chip, the operation cycle time for propagation step is 2.2 $$\upmu $$μs, and the power consumption is 363 mW at a supply voltage of 3.3 V. In experiments using this LSI chip, we have successfully generated subjective contours of Kanizsa figures.

Image compression sensor based on column parallel architecture

We propose a novel image sensor which has compression function on its sensor plane. The image compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging. The compression algorithm is based on conditional replenishment. It detects motion and encodes only the pixels in moving areas. We have been investigating pixel parallel and column parallel architectures of the image compression sensor. In this paper, we present the column parallel architecture of the proposed sensor. In this architecture, fill factor and power dissipation are comparable to conventional MOS sensors in spite of integration of the processing circuits. We have fabricated a prototype chip based on the column parallel architecture. We describe the circuit and layout design and the results of some experiments using the prototype.

Computational image sensor for on sensor compression

We propose a novel integration of image compression and sensing in order to enhance the performance of an image sensor. By integrating a compression function onto the sensor focal plane, the image signal to be read out from the sensor is significantly reduced and the pixel rate of the sensor ran consequently be increased. The potential applications of the proposed sensor are in high pixel-rate imaging, such as high frame-rate image sensing and high-resolution image sensing. The compression scheme we employ is a conditional replenishment, which detects and encodes moving areas. In this paper, we introduce two architectures for on-sensor compression; one is the pixel parallel approach and the other is the column parallel approach. We prototyped a VLSI chip of the proposed sensor based on the pixel parallel architecture. We show the design and describe the results of the experiments obtained by the prototype chip.