Pipelined Successive Approximation Register ADC Research Articles

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enables cascading multiple dynamic-amplifier-based pipeline stages. The replica-biased amplifiers from the 2nd to the last stage maintain the differential gain, eliminating the need for bit-weight calibrations. The 1st~3rd stages utilize a loop-unrolled SAR structure for high-speed conversion. A 9-bit 500MS/s pipelined SAR ADC is fabricated in 28nm CMOS process, and it achieves SNDR of 49.1dB and SFDR of 60.4dB at low frequency and SNDR of 45.3dB and SFDR 56.0dB at Nyquist frequency. The measured performance over wide input common-mode and temperature range validates the operation of the replica-biased dynamic amplifiers. The measured Walden figure of merit (FoMw) is 23.3fJ/conversion-step and Schreier FoM (FoMs) is 158.6dB, respectively.

Bandpass ΔΣ ADC using pipelined SAR ADC

This Letter proposes a second-order bandpass ΔΣ ADC using a pipelined successive-approximation-register (SAR) ADC as an internal quantiser. The second-order bandpass noise-shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure. The proposed ADC can show very high resolution even with low-order noise-shaping and low oversampling ratio. Also, it shows good energy efficiency and a high sampling rate due to the use of a pipelined SAR ADC as a quantiser.

Background calibration based on signal‐dependent dithering for pipelined SAR ADCs exploiting noise quantiser technique

A signal-dependent dithering calibration exploiting noise quantiser (NQ) technique to correct capacitor mismatch and inter-stage gain error in pipelined successive approximation register (SAR) ADCs is proposed. With signal-dependent dithering injection, capacitor mismatch and gain error are extracted and subsequently calibrated as one error in the background. Besides, a novel NQ is proposed for a dithering injection only when the residue is near the threshold of the comparator, thereby allowing the injection of dithering without consuming the dynamic range. The simulation results show that the calibration can significantly improve the performance of pipelined SAR ADCs without extra hardware overhead and timing budget.

Error shaping technique of capacitor mismatch and inter‐stage gain in noise shaping pipelined SAR ADCs

An error shaping (ES) technique in noise shaping pipelined successive approximation register (SAR) ADC is proposed to deal with capacitor mismatch and inter-stage gain errors, which is immune from the variation of the process, voltage, and temperature. By adopting data-weight average logic and delaying the reset of the second stage capacitors, all of the capacitor mismatch and inter-stage gain errors are shaped. According to the simulation, the signal-to-noise and distortion ratio and spurious free dynamic range increase by about 15 and 20 dB after ES.

Background bit‐weight calibration in pipelined successive approximation register ADC

A background bit-weight calibration in pipelined successive approximation register ADC is proposed. By exploiting the conversion results of the first stage to determine the injection of the dithered signal and introducing two extra capacitors into the first stage to reduce the range of first-stage residue, a robust and totally background calibration is implemented. According to the simulation, the signal-to-noise and distortion ratio and spurious free dynamic range are improved from 66.3 to 73.3 dB and 78.4 to 85.1 dB, respectively, after calibration.

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using Vcm-based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 V supply. The chip occupies a core area of only 0.58 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 66.7 dB and a peak spurious-free dynamic range (SFDR) of 78.6 dB at 10 MS/s sampling rate and consumes 10 mW. The figure of merit (FOM) of the proposed ADC is 0.56 pJ/conversion-step.

High‐gain and power‐efficient dynamic amplifier for pipelined SAR ADCs

A new power-efficient dynamic residue amplifier for pipelined successive-approximation-register (SAR) ADCs is presented. A complementary input pair and a reference level detection technique are proposed to improve the performance of the dynamic amplifier. At a 400 MS/s sampling rate, the proposed amplifier achieves a gain of 16. The input referred noise is 57.2 μV and the total harmonic distortion is –57.1 dB. The power consumption of the proposed amplifier is 55.6 μW in 28 nm CMOS technology.

Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μ m mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step.

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS

A two-stage pipelined SAR (Successive Approximation Register) ADC is presented. The ADC consists of a 6-bit SAR-based MDAC and a 7-bit SAR ADC with 1-bit redundancy to relax the requirement for accuracy. The zero-crossing-based circuit is introduced as a replacement for the conventional OTA. The dual-phase charge transfer technique is used to ensure high bandwidth and high accuracy of the MDAC. The prototype was fabricated in a 0.18µm standard CMOS technology. At a supply voltage of 1.8V and a sample rate of 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 66.53dB and consumes 5.5mW, resulting in a figure of merit (FOM) of 63.5fJ/conversion-step. The ADC occupies an active area of 0.44mm2.

A novel redundant pipelined successive approximation register ADC

A novel redundant pipelined successive approximation register ADC