Physics-based Electromigration Model Research Articles

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronic-based memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workload-dependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.

Reliability based hardware Trojan design using physics-based electromigration models

In recent years the concern over Hardware Trojans has come to the forefront of hardware security research as these types of attacks pose a real and dangerous threat to both commercial and mission-critical systems. One interesting threat model utilizes semiconductor physics, specifically aging effects such as Electromigration (EM). However, existing methods for EM-based Trojans rely on empirical Black's models can easily lead to performance degradation and less accuracy in Trojan activation time prediction. In this article, we study the EM-based Trojan attacks based on recently developed physics-based EM models. We propose novel EM attack techniques in which the EM-induced hydrostatic stress increase in a wire is caused by wire structure or layer changes without changing the current density of the wires. The proposed techniques consist of sink/reservoir insertion or sizing and layer switching techniques based on the early and late failure modes of EM wear-out effects. As a result, the proposed techniques can have minimal impact on circuit performance, which is in contrast with existing current-density-based EM attacks. The proposed techniques can serve as a trigger for the EM attack on power/ground networks and signal and clock networks. Furthermore, we also present two potential EM attack mitigation techniques, namely, the split fabrication and burn-in testing.

Dynamic reliability management based on resource-based EM modeling for multi-core microprocessors

This article presents a new approach for system-level reliability management for multi/many core microprocessors. In the new approach, the electro-migration (EM) induced time to failure (TTF) at the system level is modeled as a resource, which is abstracted, from a recently proposed physics-based EM model, at the chip level. In this model, a single core can spend the TTF resources at different rates specified by the temperature and the related power consumption. As a result, the new resource-based EM model allows more flexible EM-reliability management for multi/many-core systems. As an application of the new model, we propose a novel task migration method to explicitly balance consumption of EM resources for all the cores. The new method aims at equalizing the probability of failure of each core, which will maximize the lifetime of the whole multi/many core system. To more efficiently regulate the lifetime of the multi/many core system, dynamic voltage and frequency scaling (by using different performance states (p-states), which can represent different operating voltages and frequencies) is further employed to compensate for the excessively consumed lifetime of all the cores when the chip is loaded with heavy tasks for a certain period of time. In this way, the TTF of all the cores could be compensated to meet the lifetime requirement, giving the multi/many core system more flexibility to handle heavy task assignment on demand. Experimental results on a 36-core processor platform show that the proposed task migration scheme could balance the lifetime consumption of all the cores, and maintain even-distributed TTF slacks across different cores, while the existing temperature-based task migration schemes lead to diverged TTF of cores. The results also show that the TTF consumption could be easily compensated for by switching to a low p-state, which could not be achieved if TTF consumption diverged across different cores.

Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks

This paper presents a novel approach and techniques for physics-based electromigration (EM) assessment in power delivery networks of very large scale integration systems. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect branches, is considered as a failure criterion. It replaces a currently employed conservative weakest branch criterion, which does not account an essential redundancy for current propagation existing in the power-ground (P/G) networks. EM-induced increase in the resistance of the individual grid branches is described in the approximation of the recently developed physics-based formalism for void nucleation and growth. An approach to calculation of the void nucleation times in the group of branches comprising the interconnect tree is implemented. As a result, P/G networks become time-varying linear networks. A developed technique for calculating the hydrostatic stress evolution inside a multibranch interconnect tree allows to avoid over optimistic prediction of the time-to-failure made with the Blech–Black analysis of individual branches of interconnect tree. Experimental results obtained on a number of International Business Machines Corporation benchmark circuits show that the proposed method will lead to less conservative estimation of the lifetime than the existing Black–Blech-based methods. It also reveals that the EM-induced failure is more likely to happen at the place where the hydrostatic stress predicted by the initial current density is large and is more likely to happen at longer times when the saturated void volume effect is taken into account.

Electromigration assessment for power grid networks considering temperature and thermal stress effects

With technology scaling, reliability has emerged as a major design constraint for very-large-scale integrated circuits. Many prior works have investigated electromigration (EM) on full-chip power grid interconnects. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure. Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation.