Physically Unclonable Functions Instances Research Articles

Reconfigurable Physically Unclonable Functions Based on Nanoscale Voltage‐Controlled Magnetic Tunnel Junctions

AbstractWith the fast growth of the number of electronic devices on the internet of things (IoT), hardware‐based security primitives such as physically unclonable functions (PUFs) have emerged to overcome the shortcomings of conventional software‐based cryptographic technology. Existing PUFs exploit manufacturing process variations in a semiconductor foundry technology. This results in a static challenge–response behavior, which can present a long‐term security risk. This study shows a reconfigurable PUF based on nanoscale magnetic tunnel junction (MTJ) arrays that uses stochastic dynamics induced by voltage‐controlled magnetic anisotropy (VCMA) for true random bit generation. A total of 100 PUF instances are implemented using 10 ns voltage pulses on a single chip with a 10 × 10 MTJ array. The unipolar nature of the VCMA mechanism is exploited to stabilize the MTJ state and eliminate bit errors during readout. All PUF instances show entropy close to one, inter‐Hamming distance close to 50%, and no bit errors in 104 repeated readout measurements.

Experimental Examination of Component-Differentially-Challenged XOR PUF Circuits

Physical unclonable functions (PUFs), leveraging tiny physical variations of the circuits to produce unique responses for individual PUF instances, are emerging as a promising class of hardware security primitives for resource-constrained IoT devices. Component-differentially-challenged XOR PUFs (CDC XPUFs) are among the PUFs which were shown to be highly secure to machine learning modeling attacks. However, no study of implementation and experimentation has been carried out. In this paper, we report our implementations of CDC XPUFs on FPGAs and experimental studies of the essential properties of CDC XPUFs.

Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT

Remote integrity verification plays a paramount role in resource-constraint devices owing to emerging applications such as Internet-of-Things (IoT), smart homes, e-health, and so on. The concept of Virtual Proof of Reality (VPoR) proposed by Rührmair et al. in 2015 has come up with a Sense-Prove-Validate framework for integrity checking of abundant data generated from billions of connected sensors. It leverages the unreliability factor of Physically Unclonable Functions (PUFs) with respect to ambient parameter variations such as temperature, supply voltages, and so on, and claims to prove the authenticity of the sensor data without using any explicit keys. The state-of-the-art authenticated sensing protocols majorly lack in limited authentications and huge storage overhead. These protocols also assume that the behaviour of the PUF instances varies unpredictably for different levels of ambient factors, which in turn makes them hard to go beyond the theoretical concept. We address these issues in this work 1 and propose a Machine Learning (ML) assisted PUF calibration scheme to predict the Challenge-Response Pair (CRP) behaviour of a PUF instance in a specific environment, given the CRP behaviour in a pivot environment. Here, we present a new class of authenticated sensing protocols where we leverage the beneficence of ML techniques to validate the authenticity and integrity of sensor data over ambient factor variations. The scheme also reduces the storage complexity of the verifier from O ( p * K * l * ( c + r )) to O ( p * l *( c + r )), where p is the number of PUF instances deployed in the framework, l is the number of challenge-response pairs used for authentication, c is the bit lengths of the challenge, r is the response bits of the PUF, and K is the number of levels of ambient factor variations. The scheme alleviates the issue of limited authentication as well, whereby every CRP is used only once for authentication and then deleted from the database. To validate the proposed protocol through actual experiments on FPGA, we propose 5-4 Double Arbiter PUF, which is an extension of Double Arbiter PUFs (DAPUFs) as this design is more suited for FPGA, and implement it on Xilinx Artix-7 FPGAs. We characterise the proposed PUF instance from −20° C to 80° C and use Random Forest --based ML technique to generate a soft model of the PUF instance. This model is further used by the verifier to authenticate the actual PUF circuit. According to the FPGA-based validation, the proposed protocol with DAPUF can be effectively used to authenticate sensor devices across wide variations of temperature values.

Experimental Study of Component-Differentially-Challenged XOR PUFs as Security Primitives for Internet-of-Things

Security is critically important for Internet-of-Things, but existing cryptographic protocols are not lightweight enough for resource-constrained IoT devices. Implementable with simplistic circuits and operable with shallow power, physical unclonable functions (PUFs) leverage small but unavoidable physical variations of the circuit to produce unique responses for individual PUF instances, rendering themselves good candidates as security primitives for IoT devices. Component-differentially-challenged XOR PUFs (CDC XPUFs) are among the PUFs which were shown to be highly secure to machine learning modeling attacks. However, no study of implementation and experimentation has been carried out. In this paper, we report our implementations of CDC XPUFs on FPGAs and experimental studies of the essential properties of CDC XPUFs.

Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function

Physical unclonable functions (PUFs) have broad application prospects in the field of hardware security. Like faults in general-purpose circuits, faults may also occur in PUFs. Fault diagnosis plays an important role in the yield learning process. Traditional fault diagnosis methods are based on comparing the fault-free responses of a design and the failing responses of chips. However, different manufactured, fault-free PUFs with the same design have different challenge-response pairs, so PUFs do not have deterministic, fault-free responses. Hence, traditional fault diagnosis methods are unsuitable for PUFs. To effectively diagnose PUFs, this paper proposes a diagnostic challenge generation method for the typical PUF: arbiter PUF. The diagnostic challenges that can deterministically or probabilistically distinguish the suspect faults of arbiter PUFs are generated. Simulation experiments on diagnosing failing arbiter PUF instances show that all the actual fault locations are accurately included in the candidate sets, and the average number of candidate locations (i.e., diagnostic resolution) is 1.585. FPGA experiments on diagnosing real PUFs show that the diagnostic accuracy is also 1, and the average diagnostic resolution is 1.602.