Performance Of Physical Unclonable Functions Research Articles

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-Vth techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.

Heteronanostructured Field-Effect Transistors for Enhancing Entropy and Parameter Space in Electrical Unclonable Primitives.

Hardware security is not a new problem but is ever-growing in consumer and medical domains owing to hyperconnectivity. A physical unclonable function (PUF) offers a promising hardware security solution for cryptographic key generation, identification, and authentication. However, electrical PUFs using nanomaterials or two-dimensional (2D) transition metal dichalcogenides (TMDCs) often have limited entropy and parameter space sources, both of which increase the vulnerability to attacks and act as bottlenecks for practical applications. We report an electrical PUF with enhanced entropy as well as parameter space by incorporating 2D TMDC heteronanostructures into field-effect transistors (FETs). Lateral heteronanostructures of 2D molybdenum disulfide and tungsten disulfide serve as a potent entropy source. The variable feature of FETs is further leveraged to enhance the parameter space that provides multiple challenge-response pairs, which are essential for PUFs. This combination results in stably repeatable yet highly variable FET characteristics as alternative electrical PUFs. Comprehensive PUF performance analyses validate the bit uniformity, reproducibility, uniqueness, randomness, false rates, and encoding capacity. The 2D material heteronanostructure-driven electrical PUFs with strong FET-to-FET variability can potentially be augmented as an immediately deployable and scalable security solution for various hardware devices.

A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations

The physical unclonable function (PUF) is a hardware security primitive that can be used to prevent malicious attacks aimed at obtaining device information at the hardware level. The ring oscillator (RO) PUF has attracted considerable research attention. To improve the reliability of the RO PUF under voltage and temperature changes, the response of the duty-cycle (DC) PUF was obtained by comparing the duty cycle of the RO rather than the period. However, this method reduces the effective utilization of process variations, which limits its implementation in mature advanced manufacturing processes. In this study, a splitting duty-cycle (SDC) PUF was proposed to balance the effective extraction of process variations and robustness under voltage and temperature changes. The sensibility formula between the performance of SDC PUF and process, voltage, and temperature was established through a circuit model and statistical methodology, and the comprehensive characteristics of SDC PUF were analyzed theoretically. Next, 16 SDC PUFs with 128-bit responses were implemented and measured on a Xilinx Virtex-7 device. The experimental results revealed that the average native reliability of SDC PUF was 98.97%, and the reliability was 97.32% under various voltage and temperature conditions. This result revealed advantages over the DC PUF implemented in the same device. The uniqueness of the SDC PUF was 50.42%, and it passed the NIST SP 800-22 randomness and autocorrelation function tests.

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Hardware security modules play a crucial role in protecting and preserving technologically integrated systems that are used in daily life. They employ cryptographic protocols to secure a system against adversaries. Generally, cryptographic algorithms and security keys are quintessential for maintaining the security of a system. Cryptography uses a secret key to encipher and decipher the data. These secret keys are stored in a non-volatile memory that attackers can easily access. The hardware security primitive, Physical Unclonable Function (PUF) is a promising alternative for enhancing the security of interconnected devices. A PUF produces an output in response to an input based on physical structure and intrinsic manufacturing variations of an integrated circuit (IC). The generated random response being unpredictable, act as a robust secret key in cryptographic protocols. The first silicon PUF is the Arbiter PUF, which can instantly produce significantly more secret keys based on the input with a lightweight design. Due to its advantage, it is best suited for device authentication in resource-constrained applications employing the Internet of Things (IoT). The PUF is also suitable for applications such as the Internet of Vehicles, the Internet of Medical Things, RFID tags, and smart cards. In this paper, the basic Arbiter PUF design is implemented in ZedBoard to analyze the PUF performance characteristics for 16, 32, and 64-bit responses. A review of Arbiter PUF design, different compositions of Arbiter PUF, their individual characteristics, and vulnerabilities against machine-learning attacks have been presented at their broader best in this paper.

Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning

The Physical Unclonable Function (PUF) has been proposed for the identification and authentication of devices and cryptographic key generation. A strong PUF provides an extremely large number of device-specific challenge-response pairs (CRP) which can be used for authentication. Unfortunately, the CRP mechanism is vulnerable to modeling attack, which uses machine learning (ML) algorithms to predict PUF responses. Many methods have been developed to strengthen strong PUFs; however, recent studies show that they are still vulnerable under refined ML algorithms with enhanced computing power. In this article, we propose to defend PUFs against modeling attacks from a different perspective. By modifying the CRP mechanism, a PUF can provide contradictory data such that an accurate prediction model of the PUF under attack cannot be built. Three different levels of threats are analyzed, and experimental results show that the proposed method provides an effective countermeasure against ML based modeling attacks. The proposed protection mechanism is validated using FPGA, and the results show that the performance of PUFs is also improved with the help of the proposed protection mechanism. In addition, the proposed method is compatible with hardware strengthening schemes to provide even better protection for PUFs.

Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function

This paper demonstrates an implementation of physical unclonable function (PUF) using complementary organic transistors operating at low-voltage. PUF is an essential security element, and is important for various applications of organic devices. We implement a simple buskeeper PUF, which consists of two inverters. We confirm that the PUF bit values on the test chip can be read at a standard voltage for electronic circuits (3.3 V) via a standardized circuit board interface. We observed a low static current consumption (11.8 μA/90 bits) for the PUF chip. The PUF performance, chip-to-board interface performance, and requirements for the board interface in an organic transistor chip are discussed based on the measurement results of the test chip.

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design

This paper presents a design of strong physical unclonable function (PUF) exploiting the sneak paths in the resistive X-point array. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs. To eliminate the undesired collision or diffuseness in X-point PUF with “analog” resistance distribution and “digital” resistance distribution is employed in this paper. The effect of design parameters and non-ideal properties in X-point array on the performance of X-point PUF is systematically investigated by Simulation Program with Integrated Circuit Emphasis (SPICE) simulation. The simulation results show that—1) the PUF’s performance presents strong dependence on the percent of cells in the on-state, thus should be carefully optimized for the robustness against the reference current variation of the sense amplifier; 2) the interconnect resistance decreases the column current thus the reference current should scale down with the scaling of technology node; 3) larger on/off ratio is desired to achieve low power consumption and high robustness against reference current variation; and 4) the device-to-device variation might degrade the performance of X-point PUF, which can be mitigated with write-verify programming scheme in the PUF construction phase. In addition, the proposed X-point PUF presents no correlation between challenges and responses, and strong security against the possible SPICE modeling attack and machine learning attack. Compared with the conventional Arbiter PUF, the X-point PUF has benefits in smaller area, lower energy, and enhanced security.

Nano-electromechanical Switch Based on a Physical Unclonable Function for Highly Robust and Stable Performance in Harsh Environments.

A physical unclonable function (PUF) device using a nano-electromechanical (NEM) switch was demonstrated. The most important feature of the NEM-switch-based PUF is its use of stiction. Stiction is one of the chronic problems associated with micro- and nano-electromechanical system (MEMS/NEMS) devices; however, here, it was utilized to intentionally implement a PUF for hardware-based security. The stiction is caused by capillary and van der Waals forces, producing strong adhesion, which can be utilized to design a highly robust and stable PUF. The probability that stiction will occur on either of two gates in the NEM switch is the same, and consequently, the occurrence of the stiction is random and unique, which is critical to its PUF performance. This uniqueness was evaluated by measuring the interchip Hamming distance (interchip HD), which characterizes how different responses are made when the same challenge is applied. Uniformity was also evaluated by the proportion of "1" or "0" in the response bit-string. The reliability of the proposed PUF device was assessed by stress tests under harsh environments such as high temperature, high dose radiation, and microwaves.

A comprehensive set of schemes for PUF response generation

In this paper we present a comprehensive set of schemes to generate Physical Unclonable Function (PUF) IDs out of raw results generated by multiple PUF designs. Software scripts have been developed to generate the PUF IDs using five different schemes. We also propose a set of PUF metrics that are based on the Worst Case (WC) PUF performance. Values of these metrics, for the Ring Oscillator (RO) PUF and SR-Latch PUF, have been presented and analyzed in the paper. Additionally, the effect of choosing different parameters on PUF quality metrics is thoroughly analyzed.

Weighted Hamming distance for PUF performance evaluation

To analyse and compare physical unclonable function (PUF) concepts, a set of parameters should be defined to measure performance. The Hamming distance (HD) is a parameter to measure the number of different elements of two strings of the same length. In this reported research, weighted HD is proposed to evaluate and compare the performance of PUFs. The proposed parameter uses weights for calculating similarity measure. The weights can eliminate the effects of noisy responses. The proposed parameter is more efficient and has a low overhead and can be used in identification and authentication applications.