Physical Device Simulation Research Articles

Modeling and Simulations of 4H-SiC/6H-SiC/4H-SiC Single Quantum-Well Light Emitting Diode Using Diffusion Bonding Technique.

In the last decade, silicon carbide (SiC) has emerged as a potential material for high-frequency electronics and optoelectronics applications that may require elevated temperature processing. SiC exists in more than 200 different crystallographic forms, referred to as polytypes. Based on their remarkable physical and electrical characteristics, such as better thermal and electrical conductivities, 3C-SiC, 4H-SiC, and 6H-SiC are considered as the most distinguished polytypes of SiC. In this article, physical device simulation of a light-emitting diode (LED) based on the unique structural configuration of 4H-SiC and 6H-SiC layers has been performed which corresponds to a novel material joining technique, called diffusion welding/bonding. The proposed single quantum well (SQW) edge-emitting SiC-based LED has been simulated using a commercially available semiconductor device simulator, SILVACO TCAD. Moreover, by varying different design parameters, the current-voltage characteristics, luminous power, and power spectral density have been calculated. Our proposed LED device exhibited promising results in terms of luminous power efficiency and external quantum efficiency (EQE). The device numerically achieved a luminous efficiency of 25% and EQE of 16.43%, which is at par performance for a SQW LED. The resultant LED structure can be customized by choosing appropriate materials of varying bandgaps to extract the light emission spectrum in the desired wavelength range. It is anticipated that the physical fabrication of our proposed LED by direct bonding of SiC-SiC wafers will pave the way for the future development of efficient and cost-effective SiC-based LEDs.

Physical device simulation of dopant-free asymmetric silicon heterojunction solar cell featuring tungsten oxide as a hole-selective layer with ultrathin silicon oxide passivation layer

The dopant-related issues are amongst the major performance bottleneck in crystalline silicon solar cells that can be alleviated via implementation of dopant-free layers. This work presents the implementation of tungsten oxide (WOx) and titanium oxide (TiOx) as hole- and electron-selective films for heterostructure solar cell design whereby n-type Si wafer has been passivated with ultrathin silicon oxide (SiO2) layer. Several designs have been investigated including passivated hydrogenated amorphous silicon (i-a-Si:H) and characterized by evaluating work function, electron affinity, interfacial charge, and layer thickness. The high work function of WOx induces significant upward band bending to permit holes transportation towards anode, whereas, low electron-affinity for TiOx reduces the barrier against electrons at the cathode. Smaller band offsets have been observed against minority carriers for devices that employ passivated i-a-Si:H film. However, incorporating SiO2 significantly improves the energy barrier height against minority carriers that leads to an enhancement in electric field along with reduction in recombination. The best-performance device with an optimum SiO2 thickness of 1 nm numerically validated Voc of 751 mV, Jsc 40.2 mA/cm2, FF 79.7%, and η of 24.06%. A comparative analysis with hole-selective vanadium oxide (V2Ox) demonstrated η of 21.73% limited by the low work function of V2Ox.

The Effect of Align Parameter on Scattering Parameter for Pseudomorphic High Electron Mobility Transistor

In this paper, various physical device simulation of pseudomorphic High Electron Mobility Transistos are realized to show the effect of align parameter on scattering parameters. S parameters are complex numbers,so both real and imaginer part of scattering parameters are plotted with respect to frequency at different align parameters. In all figures, a brief explanation about the change of S parameter with respect to frequency and align parameter are provided. The effect of align parameter, which has a value of 0.4 differ from other align parameter values such as 0.45, 0.5, 0.55 and 0.6 on scattering parameters of the tranistor structure.

Current-Assisted SPAD with Improved p-n Junction and Enhanced NIR Performance.

Single-photon avalanche diodes (SPADs) fabricated in conventional CMOS processes typically have limited near infra-red (NIR) sensitivity. This is the consequence of isolating the SPADs in a lowly-doped deep N-type well. In this work, we present a second improved version of the “current-assisted” single-photon avalanche diode, fabricated in a conventional 350 nm CMOS process, having good NIR sensitivity owing to 14 μm thick epilayer for photon absorption. The presented device has a photon absorption area of 30 × 30 µm2, with a much smaller central active area for avalanche multiplication. The photo-electrons generated in the absorption area are guided swiftly towards the central area with a drift field created by the “current-assistance” principle. The central active avalanche area has a cylindrical p-n junction as opposed to the square geometry from the previous iteration. The presented device shows improved performance in all aspects, most notably in photon detection probability. The p-n junction capacitance is estimated to be ~1 fF and on-chip passive quenching with source followers is employed to conserve the small capacitance for bringing monitoring signals off-chip. Device physics simulations are presented along with measured dark count rate (DCR), timing jitter, after-pulsing probability (APP) and photon detection probability (PDP). The presented device has a peak PDP of 22.2% at a wavelength of 600 nm and a timing jitter of 220 ps at a wavelength of 750 nm.

Modelling the static on-state current voltage characteristics for a 10 kV 4H–SiC PiN diode

A 10 kV 4H–SiC epitaxial PiN diode is fabricated and the measured static on-state current voltage characteristics are used to tune the physical models and parameters included in TCAD device simulations. From the measurements it is found that the on-state voltage drop decreases more than 0.5 V at a current density of 100 A/cm2, as the temperature is raised from room temperature to 300 °C. The steep slope of the IV-curve is, furthermore, maintained at elevated temperatures in contrast to most silicon PiN structures, where the decrease in mobility at higher temperatures typically decreases the IV slope, resulting in an increased voltage drop. Physical device simulations, involving common models for bandgap, incomplete ionization, charge carrier lifetime and mobility, are systematically compared and optimized to obtain the best fit with measured data. The negative temperature dependence can be simulated with good precision although the fitting is very sensitive to the choice of mobility models and, in particular, the acceptor ionization energy.

Simulation analysis of a high efficiency GaInP/Si multijunction solar cell

The solar power conversion efficiency of a gallium indium phosphide (GaInP)/silicon (Si) tandem solar cell has been investigated by means of a physical device simulator considering both mechanically stacked and monolithic structures. In particular, to interconnect the bottom and top sub-cells of the monolithic tandem, a gallium arsenide (GaAs)-based tunnel-junction, i.e. GaAs(n+)/GaAs(p+), which assures a low electrical resistance and an optically low-loss connection, has been considered. The J–V characteristics of the single junction cells, monolithic tandem, and mechanically stacked structure have been calculated extracting the main photovoltaic parameters. An analysis of the tunnel-junction behaviour has been also developed. The mechanically stacked cell achieves an efficiency of 24.27% whereas the monolithic tandem reaches an efficiency of 31.11% under AM1.5 spectral conditions. External quantum efficiency simulations have evaluated the useful wavelength range. The results and discussion could be helpful in designing high efficiency monolithic multijunction GaInP/Si solar cells involving a thin GaAs(n+)/GaAs(p+) tunnel junction.

Slot-Die-Printed Two-Dimensional ZrS3 Charge Transport Layer for Perovskite Light-Emitting Diodes.

Liquid-phase exfoliation of zirconium trisulfide (ZrS3) was used to produce stable and ready-to-use inks for solution-processed semiconductor thin-film deposition. Ribbon-like layered crystals of ZrS3 were produced by the chemical vapor transport method and were then exfoliated in three different solvents: dimethylformamide, ethanol, and isopropyl alcohol. The resulting ZrS3 dispersions were compared for stability and the ability to form continuous films on top of the perovskite layer in light-emitting diodes with the ITO/PEDOT:PSS/MAPbBr3/2D-ZrS3/LiF/Al structure. Film deposition was performed by using either spray or slot-die coating methods. The slot-die coating route proved to produce better and more uniform films with respect to spray coating. We found that the 2D ZrS3 electron injection layer (EIL) stabilized the interface between the perovskite and LiF/Al cathode, reducing the turn-on voltage to 2.8 V and showing a luminance that does not degrade during voltage sweep. On the other hand, EIL-free devices show electroluminescence on the first voltage sweep that reduces almost to zero in the subsequent sweeps. Combining physical device simulation and density functional theory calculation, we are able to explain these results in terms of lowering the electron injection barrier at the cathode.

Analysis of I–V–T Characteristics of Au/n-InP Schottky Barrier Diodes with Modeling of Nanometer-Sized Patches at Low Temperature

The current–voltage (I–V) characteristics of inhomogeneous Au/n-InP Schottky barrier (SB) diodes have been investigated in the temperature range of 100 K to 300 K, and detailed numerical simulation study carried out using a physical device simulator. The experimental I–V curves for the diode in both forward- and reverse-bias conditions were fit to explain the current transport mechanisms at low temperature. Tunneling current flows through the native oxide and nanometer-sized patches embedded at the Au/n-InP interface. These patches result in a lower (local) barrier height which is temperature dependent and responsible for the diode current behaviors in the low-bias regime. The patch area is on the order of one-millionth of the total diode area, and the SB is between 0.01 eV and 0.3 eV in the patch region. The simulation results are in good agreement with the measurements in the whole explored current range extending over six orders of magnitude.

Enhanced front-illuminated p-i-p-i-n GaN/AlGaN ultraviolet avalanche photodiodes

We proposed an improved front-illuminated GaN/AlGaN separate absorption and multiplication (SAM) ultraviolet avalanche photodiode (APD) based on physical analysis and device simulations. By inserting an Al0.2Ga0.8N p-type layer into the p-i-p-i-n APD structure, a built-in electric field resulted from polarization effect will be introduced to facilitate the transport of electrons from absorption layer to multiplication region. The enhanced heterostructure APD presents significantly higher multiplication gain compared with the homogeneous one. Moreover, the doping concentration and thickness of the interlayer were optimized according to device performances, because the interlay has important effects on the electric field distribution and energy-band profile of the front-illuminated SAM APD.

Absence of Evidence for Fixed Charge in Metal–Aluminum Oxide–Silicon Tunnel Diodes

Here, a controlled variation in the fixed charge density (NF) and thickness of aluminum oxide tunnel insulators is reported, and the impact on Schottky barrier height in metal–insulator–semiconductor (MIS) diodes is studied. Analysis of metal–aluminum oxide–silicon capacitor structures indicates a change in NF from +1 × 1012 cm−2 in as‐deposited films to −2 × 1012 cm−2 in annealed films. An analytical model and numerical device physics simulations are used to predict changes in ­based on these changes in NF and alumina thickness. Surprisingly, Mott–Schottky derived values did not follow the trends predicted by these electrostatic models. In fact, there seems to be no discernable effect of NF in diodes with alumina thicknesses below 2 nm, contrary to contactless measurements of the fixed charge of films of similar thickness. The trends are better explained by a dipole model. It is further shown that in as‐deposited MIS diodes, the dipole is a function of alumina layer thickness, whereas in annealed MIS diodes, the dipole and were roughly constant independent of alumina thickness. These data suggest a strategy by which the of MIS tunnel contacts can be controlled and which has implication for the design of electrical contacts.

Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes

A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

Electrically Driven Insulator–Metal Transition-Based Devices—Part I: The Electrothermal Model and Experimental Analysis for the DC Characteristics

We present a device model for the electrically driven insulator-to-metal transition (E-IMT) that captures the essential physics in E-IMT and can be used for physical device simulations and mixed-mode simulations of circuits containing IMT elements. Aspects of the model include the temperature-dependent resistivity, Joule heating, heat transport, and the spatial and dynamic coupling of the above phenomenon. We show that the model captures the dc and transient characteristics as measured by experiments. The model points out the existence of two critical transition voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) under bidirectional sweep, the physical origin of this hysteresis, and correctly predicts the scaling of the critical voltage for transition V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> with the device size. The models' effectiveness as a basis for developing a mixed-mode circuit simulator is shown via comparison with experimental data for a steep-swing hybrid-field-effect transistor.

Local 2DEG Density Control in Heterostructures of Piezoelectric Materials and Its Application in GaN HEMT Fabrication Technology

This paper investigates the local control of two dimensional electron gas (2DEG) density in AlGaN/GaN heterostructures by applying external mechanical stress. The proposed 2DEG tuning mechanism relies on a local modification of the piezoelectric contribution to the total 2DEG concentration at an AlGaN/GaN heterostructure interface. Discontinuities of internally stressed passivation films are known to locally modify mechanical stress in their vicinity and may, therefore, transfer mechanical strain to neighboring device regions. If a mechanically stressed passivation laterally terminates at a gate trench on top of a GaN/AlGaN heterojunction, it will, therefore, induce mechanical strain into the semiconductor at the location of the trench sidewalls. This locally affects the piezoelectric polarization vector and, thus, changes 2DEG concentration in this region. As this effect directly modifies electronic properties underneath the gate electrode, a shift of threshold voltage will be the consequence. This phenomenon has been investigated by coupling mechanical and physical device simulation and by experimental verification of the simulation results. Finally, as one of the several possible application examples, normally-off (E-mode) and normally-on (D-mode) transistors were monolithically integrated on the same wafer by embedding the respective gate electrodes into passivation layers with different degrees of mechanical stress. DC measurements of the obtained transistors showed competitive performance levels.

Limits of Contact Selectivity/Recombination on the Open-Circuit Voltage of a Photovoltaic

We analytically calculate fundamental limits on the open-circuit voltage (Voc) of a solar cell imposed by contact selectivity and contact recombination. To do so, we consider a simple model consisting of only carrier generation in an absorber and charge transfer to its contacts enabling an algebraic solution for the relevant partial currents and the calculation of a contact-determined Voc. An expression for Voc is determined assuming the partial currents at the contacts linearly depend on the product of the appropriate equilibrium exchange current density and excess carrier concentration at the contact. Quantitatively defining contact selectivity and contact recombination, we illustrate the roles of the exchange current densities, recombination, and selectivity on Voc. Additionally, we use complete device physics simulations to show that our simplified model is valid in practically relevant situations. The framework we have developed elucidates the physics underlying more qualitative discussions of select...

Physical modelling and experimental characterisation of InAlAs/InGaAs avalanche photodiode for 10 Gb/s data rates and higher

InAlAs/InGaAs avalanche photodiodes (APD) were simulated using physical device models, then designed and fabricated to detect light in the wavelength range from 1.3 to 1.55 µm. DC characterisation under dark and light conditions were performed at room temperature to measure and investigate the performance of the APD. High-frequency characterisation was carried out on the device to extract the diode intrinsic and extrinsic parameters. The work reported here focuses on the dark and light physical device simulations (both under DC and AC conditions) which were accomplished using Atlas SILVACO tool. The effect of electron velocity overshoot was considered for accurate bandwidth modelling. All measured data are in excellent agreement with the modelled ones. The internal device gain of the APD is 45 at −23.5 V leading to a ∼220 GHz gain–bandwidth product. This successful APD model can be exploited to further improve the diode structure for higher data rate applications beyond 10 Gb/s.

Breakdown and optical response of CMOS perimeter gated single‐photon avalanche diodes

The breakdown and optical response of perimeter gated single-photon avalanche diodes fabricated in a standard 0.5 μm 2-poly 3-metal CMOS process is presented. These diodes prevent premature edge breakdown through the addition of a polysilicon gate. The fabricated devices feature varying size, shape (square, octagonal, and circular), and junction types (nwell-p+ and psub-nwell) with a perimeter gate located on top of the junction. Voltage applied to the gate modulates the electric field and its effect on the breakdown voltage and optical response is discussed. Experimental results are supported by physical device simulations where applicable.

Performance enhancement of AlGaN/InGaN MQW LED with GaN/InGaN superlattice structure

A gallium nitride (GaN)-based light-emitting diode (LED) structure with 10-period superlattice layers (SLs) of p -GaN/i -In0.2 Ga0.8 N, inserted between p -GaN and 12-period Al0.16 Ga0.84 N/In0.2 Ga0.8 N multiple quantum well (MQW) layers, is numerically designed and examined using physical device simulator, SILVACO. The SL structure acts as a confinement layer of holes that serves to mitigate the effects of efficiency droop and leakage current within LED. Consequently, inserting SL structure within epitaxial domain tends to improve the current-spreading capability of the device. The proposed structure is compared with the conventional LED without SL and enhanced LED performance has been demonstrated by the SL-based device. The measured power spectral density and luminous power of the under-investigated device are 8.27 W/cm eV at 433 nm and 3.1 W/cm at 12.32 kA/cm2, respectively. Correspondingly, the external QE of 25.4% has been determined that is higher than the earlier LED reported with 10-period SL structure of p -GaN/i -In0.2 Ga0.8 N and 12-period MQWs of GaN/indium GaN configuration. Moreover, another structure based on 30-period SL was also investigated and the output results exhibited no significant improvement in the efficiency due to thermionic emission and thickness-induced strain factors.

The Effect of Pinned Photodiode Shape on Time-of-Flight Demodulation Contrast

An empirical investigation on improving the pinned photodiode (PPD) demodulation contrast by tailoring the geometry of the device is presented. Results of this TCAD simulation-based study are used to develop a structure especially suited for time-of-flight applications. In order to obtain a fair comparison between various PPD shapes, a square structure is adopted as a benchmark and all subsequent PPD geometries use the same process parameters. Five different PPD shapes are compared: 1) nominal square-shaped PPD; 2) triangular PPD; 3) constant-field PPD; 4) L-shaped constant-field PPD; and 5) proposed PPD. Device physics simulations are undertaken and the speed of each structure is evaluated on the basis of its demodulation contrast. It is shown that triangular and constant-field PPDs can provide significant improvement compared with a conventional square-shaped PPD, however they still lack effective lateral charge transfer in the final electron sorting stage. The final PPD proposed in this paper achieves this with a tailored PPD shape and doping gradient. In addition, the transfer gates are placed close to one another to make use of gate-induced fringe fields and thus improve the speed of electron sorting. Using these techniques, a PPD demodulation contrast of 61% is obtained at a frequency of 100 MHz, which is comparable to the contrast achieved in state-of-the-art photogate-based designs.

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150°C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult to implement and to verify during the design of a complex Smart Power circuit. These rules are often based on the physical device simulations or on the empirical results extracted from predefined benchmark structures. In this paper, a novel approach is proposed for designing robust circuits integrating accurate and specific analysis of substrate couplings already into the design flow. First, substrate currents injected by power transistors are discussed to show the spatial distribution of voltage and currents into the substrate. A set of guidelines to optimize substrate currents is presented as a summary of the studied test cases. Then, an H-Bridge output driver was implemented in a $0.35$ - $\mu$ m HVCMOS technology to investigate substrate currents by both measurements and simulations. Reverse currents were deliberately injected into the chip to activate substrate lateral and vertical parasitic bipolar junction transistors and measured data closely match circuit simulation results in both cases.