In the early VLSI design stages, as most interest is given to timing closure, various techniques are deployed to satisfy the timing constraints and close design timing. Nevertheless, timing still needs to be accurate at the early stages due to the lack of physical design information. Therefore, the challenge for most EDA Logic Synthesis engines is to improve the overall timing accuracy at higher levels of abstraction. In this paper, we shall reduce the error gap in Cell Delay estimation for a placed gate-level netlist. We will generate the post-placed netlist from two different Siemens EDA tools. The purpose is to improve the accuracy of the cell delays of Oasys-RTL Synthesis tool, based on accurate cell delays from Aprisa PnR. We have trained and tested various Machine Learning models on several 16 nm designs. We achieved the highest accuracy using the Random Forest model, where the average accuracy is 91.25%. Furthermore, as the accuracy of the Cell delay is improved, the average Root-Mean-Square-Error (RMSE) is reduced from 16.958 to 4.469.