Physical-based Analytical Model Research Articles

A Physical-Based Analytical Model for the Kink Current of Polycrystalline Silicon TFTs

A physical-based analytical kink current model for polycrystalline -silicon (poly-Si) thin-film transistors (TFTs) has been proposed. Two important mechanisms for the kink current, namely carrier impact ionization and the parasitic bipolar junction transistor effect, are physically included in the model without introducing any artificial parameters. The proposed kink current model is fully compatible with existing ON-state drain current models of poly-Si TFTs. Model parameter extraction procedure is presented, which is based on a group of output characteristics of poly-Si TFTs with different channel lengths. The model prediction straightforwardly calculated with a set of extracted parameters is verified by excellent agreement with experimental output characteristics measured from TFTs over a range of channel lengths and gate voltages.

Physical-Based Analytical Model of Amorphous InGaZnO TFTs Including Deep, Tail, and Free States

Amorphous InGaZnO (a-IGZO) is a candidate material for thin-film transistors (TFTs) owing to its large electron mobility and good uniformity over large area. a-IGZO TFTs drain current models are essential for further pushing both a-IGZO TFTs technology and circuit design. In this paper, we propose a simple physical-based and analytical model of the drain current of a-IGZO TFTs. The model is valid in both non degenerate and degenerate conduction and it accounts for deep interface states, tail localized states, and free delocalized band states. The model is validated with the measurements of both coplanar and staggered a-IGZO TFTs. It provides key physical and material parameters of the transistor and, owing to its class $C^{\infty }$ formulation, it can be straightforwardly implemented in circuit simulators.

Accurate Model for the Threshold Voltage Fluctuation Estimation in 45-nm Channel Length MOSFET Devices in the Presence of Random Traps and Random Dopants

A physical-based analytical model to predict the fluctuations in threshold voltage induced by a single interface trap at a random location along the channel in a typical sub-50-nm MOSFET is of utmost significance. In this letter, simulation results from two different analytical models and particle-based device ensemble Monte Carlo schemes are used to compute threshold voltage variation in the presence of interface traps at a certain location in the channel. These results provide clear evidence that, without the accurate short-range Coulomb force correction, the analytical models will provide inconsistent VT for traps located near the source of the MOSFET device with 32-nm effective channel length.

A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications

A physical-based analytical model for hot-carrier induced saturation current degradation of p-MOSFET's

The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An accurate aging model for the saturation current is essential for the modeling of the CMOS inverter degradation. In this paper, we report that the saturation current degradation proceeds logarithmically in stress time. A physical analytical model, based on the pseudo-two-dimensional model, is derived for the first time to describe the saturation current degradation under various stress and measurement conditions. There are no empirical parameters in the model. Two physical parameters, the capture cross section and the density of states of electron traps, can be determined independently from the measured degradation characteristics. The simple expression is highly recommended for the modeling of the degradation of the digital CMOS circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>