Photonic Interconnection Networks Research Articles

Metal-printing tunable interlayer waveguide coupler using low-loss fluorinated polycarbonate.

Tunable three-dimensional (3D) integrated optical waveguide chips with optical interconnection function are beneficial to expand the application of optical devices in a 3D integrated photonic module. Here, we propose a thermo-optic (TO) tunable interlayer waveguide coupler based on the metal-printing technique. Low-loss fluorinated polycarbonate (AF-Ali-PC MA) and poly (methyl methacrylate-glycidyl methacrylate) [P(MMA-co-GMA)] are synthesized as waveguide core and cladding layer, respectively. The thermal stability and optical adsorption characteristics of AF-Ali-PC MA are analyzed. Optical signal transmission features of the interlayer coupling waveguides are simulated. The optical response properties and fabrication process flows of a dynamic multilayer waveguide chip can be greatly improved by the metal-printing technique. The on-off time of the TO interlayer coupling chip is obtained as 250 µs, and the electrical power consumption is measured as 7.6 mW. To the best of our knowledge, this is the first time that a TO tunable interlayer waveguide coupler is achieved by an efficient metal-printing method, which is suitable for large-scale photonic integrated circuit (PIC) systems and multilayer optical interconnection (OXC) networks.

Silicon Photonics for Extreme Scale Systems

High-performance systems are increasingly bottlenecked by the growing energy and communications costs of interconnecting numerous compute and memory resources. Recent advances in integrated silicon photonics offer the opportunity of embedding optical connectivity that directly delivers high off-chip communication bandwidth densities with low power consumption. This paper reviews the design and integration of silicon photonic interconnection networks that address the data-movement challenges in high-performance systems. Beyond alleviating the bandwidth/energy bottlenecks, embedded photonics can enable new disaggregated architectures that leverage the distance independence of optical transmission. This review paper presents some of the key interconnect requirements to create a new generation of photonic architectures for extreme scale systems, including aggregate bandwidth, bandwidth density, energy efficiency, and network resources utilization.

Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks

As the number of on-chip processor cores increases, power-efficient solutions are sought for data communication between cores. The Helix-h non-blocking photonic switch is developed to improve physical-layer and network performance parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Traffic benchmarks and practical case studies using a cycle-accurate simulation environment indicate significantly reduced insertion loss providing improved bandwidth density and scalability to manycore plurality. Improvements in system performance parameters are quantified for network bandwidth, transmission efficiency, and latency in popular photonic internconnection topologies, in comparison to previous switch designs. For instance, utilizing the Helix-h switch in a mesh topology, the bandwidth is increased by 112 percent compared to the previously highest performing switch design. Execution time and energy efficiency are improved by up to 92 and 99 percent, respectively, for representative multicore applications. Finally, the technique is generalized to a novel graph-theoretic method for articulating blocking conditions in photonic switches.

Silicon Photonics for Exascale Systems

With the extraordinary growth in parallelism at all system scales driven by multicore architectures, computing performance is increasingly determined by how efficiently high-bandwidth data is communicated among the numerous compute resources. High-performance systems are especially challenged by the growing energy costs dominated by data movement. As future computing systems aim to realize the Exascale regime-surpassing 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> operations per second-achieving energy efficient high-bandwidth communication becomes paramount to scaled performance. Silicon photonics offers the possibility of delivering the needed communication bandwidths to match the growing computing powers of these highly parallel architectures with extremely scalable energy efficiency. However, the insertion of photonic interconnects is not a one-for-one replacement. The lack of practical buffering and the fundamental circuit switched nature of optical data communications require a holistic approach to designing system-wide photonic interconnection networks. New network architectures are required and must include arbitration strategies that incorporate the characteristics of the optical physical layer. This paper reviews the recent progresses in silicon photonic based interconnect devices along with the system level requirements for Exascale. We present a co-design approach for building silicon photonic interconnection networks that leverages the unique optical data movement capabilities and offers a path toward realizing future Exascale systems.

Wavelength Locking and Thermally Stabilizing Microring Resonators Using Dithering Signals

The bandwidth bottleneck looming for traditional electronic interconnects has driven the consideration of optical communications technologies as realized through the complementary metal-oxide-semiconductor-compatible silicon nanophotonic platform. Within the silicon photonics platform, silicon microring resonators have received a great deal of attention for their ability to implement the critical functionalities of an on-chip optical network while offering superior energy-efficiency and small footprint characteristics. However, silicon microring-based structures have a large susceptibility to fabrication errors and changes in temperature. Integrated heaters that provide local heating of individual microrings offer a method to correct for these effects, but no large-scale solution has been achieved to automate their tuning process. In this context, we present the use of dithering signals as a broad method for automatic wavelength tuning and thermal stabilization of microring resonators. We show that this technique can be manifested in low-speed analog and digital circuitry, lending credence to its ability to be scaled to a complete photonic interconnection network.

On-Chip Photonic Interconnects: A Computer Architect's Perspective

As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection applications. Photonics, which has a fundamentally different mechanism of signal propagation, offers the potential to not only overcome the drawbacks of electrical signaling, but also enable the architect to build energy efficient, scalable systems. The purpose of this book is to introduce computer architects to the possibilities and challenges of working with photons and designing on-chip photonic interconnection networks. Table of Contents: List of Figures / List of Tables / List of Acronyms / Acknowledgments / Introduction / Photonic Interconnect Basics / Link Construction / On-Chip Photonic Networks / Challenges / Other Developments / Summary and Conclusion / Bibliography / Authors' Biographies

Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks

We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap.

40-Gb/s DPSK Data Transmission Through a Silicon Microring Switch

We experimentally demonstrate switching of a 40-Gb/s differential-phase-shift-keyed (DPSK) signal through a coupled silicon photonic microring switch. By simultaneously electro-optically biasing both microring cavities, we achieve 14-dB extinction ratio for signals egressing from both output ports of the switch. Packetized transmission of the 40-Gb/s DPSK signal is achieved with power penalties of 0.6 and 2.4 dB for through port and drop port signals, respectively. The effects of a coupled silicon microring are investigated, showing a broad bandwidth and a linear phase response for the drop port are necessary characteristics for routing 40-Gb/s data through the switch for photonic interconnection networks.

Photonic Interconnection Network Architectures Using Wavelength-Selective Spatial Routing for Chip-Scale Communications

The overall performance of modern computing systems is increasingly determined by the characteristics of the interconnection network used to provide communication links between on-chip cores and off-chip memory. Photonic technology has been proposed as an alternative to traditional electronic interconnects because of its advantages in bandwidth density, latency, and power efficiency. Circuit-switched photonic interconnect topologies take advantage of the optical spectrum to create high-bandwidth transmission links through the transmission of data channels on multiple parallel wavelengths; however, this technique suffers from low path diversity and high setup time overhead, which induces high network resource contention, unfairness, and long latencies. This work improves upon the circuit-switching paradigm by introducing the use of on-chip wavelength-selective spatial routing to produce multiple logical communication layers on a single physical plane. This technique yields higher path diversity in photonic interconnection networks, demonstrating as much as 764% saturation bandwidth improvement with synthetic traffic and as much as 89% improvement in execution time and energy dissipation for traffic from scientific application traces.

A Generic Optical Router Design for Photonic Network-on-Chips

Photonic network-on-chip (NoC) architectures are emerging as a new paradigm to interconnect a large number of processing cores at chip level, meeting the pressing demand for extremely high bandwidth and low power consumption. Optical routers, which are typically composed of silicon waveguides and optical switches, play a key role in an on-chip photonic interconnection network. In this paper, we propose a micro-ring-resonator (MRR)-based, scalable, and non-blocking passive optical router design, namely the generic wavelength-routed optical router (GWOR). We first introduce the four 4 × 4 GWOR router structures and then show how to construct GWORs of larger sizes by using the proposed 4 × 4 GWORs as the primitive building blocks. The number of MRRs used in the proposed GWOR is the least among the existing passive router designs for the same network size. In addition, we show that the power loss experienced on GWORs is lower than other comparative designs. Furthermore, to improve the bandwidth and fault tolerance capability of the GWORs, the redundant GWOR (RGWOR) structure is presented. RGWOR can provide multiple routing paths between each pair of input-output ports by cascading different types of GWORs.

Wavelength-selective 4×4 nonblocking silicon optical router for networks-on-chip

We design and fabricate a wavelength-selective nonblocking 4 × 4 silicon optical router based on microring resonator for use in future integrated photonic interconnection networks. We successfully demonstrate 12 possible I/O routing paths and present 13 nonblocking operating states, including four broadcasting states, with worst-case extinction ratio and cross talk of 21.05 and -21.56 dB, respectively. Thermal tuning is employed to compensate the resonance shift of microring resonators caused by fabrication errors and adjust the resonance to match the International Telecommunication Unit grid with the channel spacing of 100 GHz.

DPSK Transmission Through Silicon Microring Switch for Photonic Interconnection Networks

We experimentally demonstrate for the first time switching of differential-phase-shift-keyed (DPSK) signals through a silicon photonic electrooptic microring switch. DPSK format has been shown to be robust to nonlinear effects, and has 3-dB improved receiver sensitivity with balanced detection compared to the on-off-keyed format. Moreover, an extension to multilevel phase-shift-keyed (PSK) format enables higher data bandwidth. Packetized transmissions of single- and multichannel 10-Gb/s DPSK signals are demonstrated. Error-free transmission and power penalties of less than 1.7 dB are achieved for all the examined wavelength channels, confirming format transparency of the microring switch for PSK format, and validating the use of DPSK signaling for photonic interconnection networks.

Energy-Efficient Error Control for Tightly Coupled Systems Using Silicon Photonic Interconnects

Future computer systems will require new levels of computing power and hence new levels of core and chip densities. Because of constraints on power and area, optical interconnection networks will play a critical role in these new systems. In this paper, we describe the macrochip, a multi-chip node with an embedded silicon photonic interconnection network that consists of thousands of optical links. For such a large-scale wavelength division multiplexing optical network, we show how to use an energy-efficient error control scheme employing variable-length cyclic redundancy check codes to achieve a desirable residual bit error rate (BER) of 10−23 for reliable system operation with the individual link BER at 10−12 or higher. We use a discrete-event network simulation of the macrochip using uniform random traffic to show that our scheme incurs minimal impact on performance compared to a perfect system with no error control. Using link level energy efficiency and network throughput analysis, we estimate and report network level energy efficiency using the metric of energy per useful bit.

Scalable Photonic Interconnection Network With Multiple-Layer Configuration for Warehouse-Scale Networks

A scalable and flexible photonic interconnection network architecture suitable for warehouse-scale networks is proposed. The architecture comprises three functional layers: physical, optical, and logical layers. The network topologies achieved at the layers are tree in the physical layer; hypercube in the optical layer; and relatively lower dimensional topologies like two-dimensional mesh, tree, and ring in the logical layer. The application of the appropriate network configuration in each layer by making good use of wavelength division multiplexing technology realizes a truly scalable and flexible network. Evaluation of the physical link requirements reveals the scalability of the proposed network architecture.

Architectural Exploration of Chip-Scale Photonic Interconnection Network Designs Using Physical-Layer Analysis

We conduct an architectural exploration of three chip-scale photonic interconnection networks in a novel simulation environment, exploring insertion loss, crosstalk, and energy. The impact of these metrics is evaluated in the context of network performance.

Cascaded Microresonator-Based Matrix Switch for Silicon On-Chip Optical Interconnection

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper reviews developments in cascaded microresonator-based matrix switches for silicon photonic interconnection networks in many-core computing applications. Specifically, we emphasize our recently proposed 5 <formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> 5 matrix switch comprising two-dimensionally cascaded microring resonator-based electrooptic switches coupled to a waveguide cross-grid on a silicon chip. The cross-grid adopts low-loss low-crosstalk multimode-interference-based waveguide crossings. Such a microresonator-based matrix switch offers nonblocking interconnections among multiple inputs and multiple outputs, with the key merits of i) a tens to hundreds of micrometers-scale footprint, ii) gigabit/second-scale data transmission, iii) nanosecond-speed circuit-switching, iv) 100-<formula formulatype="inline"><tex Notation="TeX">$ \mu{\hbox{W}}$</tex></formula>-scale dc power consumption per link, and v) large-scale integration for networks-on-chips applications. We analyze in detail the microring resonator-based cross-grid switch design for high-data-rate signal transmission in the context of our proposed 5 <formula formulatype="inline"> <tex Notation="TeX">$\times$</tex></formula> 5 matrix switch. We also study the feasibility of large-scale integration of the matrix switch. We report proof-of-concept experiments of a single cross-grid switch element and a 2 <formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> 2 matrix switch, propose design guidelines, and discuss future engineering challenges. </para>

Scalable optical switches for computing applications [Invited

A scalable photonic interconnection network architecture is proposed whereby a Clos network is populated with broadcast-and-select stages. This enables the efficient exploitation of an emerging class of photonic integrated switch fabric. A low distortion space switch technology based on recently demonstrated quantum-dot semiconductor optical amplifier technology, which can be operated uncooled, is used as the base switch element. The viability of these switches in cascaded networks is reviewed, and predictions are made through detailed physical layer simulation to explore the potential for larger-scale network connectivity. Optical signal degradation is estimated as a function of data capacity and network size. Power efficiency and physical layer complexity are addressed for high end-to-end bandwidth, nanosecond-reconfigurable switch fabrics, to highlight the potential for scaling to several tens of connections. The proposed architecture is envisaged to facilitate high-capacity, low-latency switching suited to computing systems, backplanes, and data networks. Broadband operation through wavelength division multiplexing is studied to identify practical interconnection networks scalable to 100 Gbits/s per path and a power consumption of the order of 20 mW/(Gbits/s) for a 64×64 size interconnection network.

Optical 4x4 hitless slicon router for optical networks-on-chip (NoC)

We demonstrate here a spatially non-blocking optical 4x4 router with a footprint of 0.07 mm(2) for use in future integrated photonic interconnection networks. The device is dynamically switched using thermo-optically tuned silicon microring resonators with a wavelength shift to power ratio of 0.25nm/mW. The design can route four optical inputs to four outputs with individual bandwidths of up to 38.5 GHz. All tested configurations successfully routed a single-wavelength laser and provided a maximum extinction ratio larger than 20 dB.

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget. A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.

Hierarchical clustering of the data vortex optical interconnection network

The data vortex photonic interconnection network is studied for application to clustering and hierarchical layering of nodes. Performance is examined for varying cluster counts and under loads of varying network locality. In today's technology, similar performance is attained at high network communication locality loads (&gt;2/3), and a 19% latency reduction is obtained at the highest locality loads (&gt;95%) for current optical switching technology. For projected future technology, the clustered system is shown to yield up to a 55% reduction in latency for applications with 2/3 or better locality.