Phase-shifted Pulse-width Modulation Method Research Articles

Switched-Capacitor-Based Hybrid Clamped Converter for Wide Power Factor Applications

The clamped multilevel converter generally adopts the zero-sequence voltage injection method to realize the voltage balancing of the DC link capacitors. However, the relationship between the reference modulation voltage and the duty ratio of phase neutral point current is often a triangle or trapezoidal function. When the power factor is low, the required optimal zero-sequence voltage will be out of bounds, which will lead the capacitor voltage ripples to become larger or even divergent. Therefore, a novel switched-capacitor-based hybrid clamped(SCB-HC) converter is proposed in this article. The new redundant switching states are obtained by introducing the boost characteristics of the switched-capacitor(SC) circuit. And a hybrid phase-shifted pulse width modulation(PS-PWM) is developed to extend its functional relationship. This ensures the peak current that flow out of the neutral points is fewer, then the capacitor voltage drift is reduced significantly. Moreover, the proposed hybrid PS-PWM method not only ensures that SC circuit switches series and parallel patter once during a carrier period, but also achieves the voltage balancing of SC and DC link midpoint capacitor naturally under ideal conditions. On top of that, the capacitor voltage balancing method is designed to ensure independent and decoupled control of all capacitor voltages. Simulations and experiments show that the proposed topology, modulation method and voltage control method are practical and feasible for wide power factor applications.

Performance improvement of cascaded H-bridge multilevel inverters with modified modulation scheme

This study proposes a modified modulation scheme based on the phase-shifted pulse-width modulation (PS-PWM) method to improve the output performance and reduce the switching loss in cascaded H-bridge multilevel inverters. The PS-PWM method is one of the most popular modulation schemes. However, it generates significant switching loss, which can lead to the failure of power semiconductor switches. Various studies have proposed modulation schemes to reduce switching loss. The clamped discontinuous PWM (DPWM) method achieves the best switching loss reduction performance in comparison with other modulation schemes. However, the clamped DPWM method has low output characteristics, such as total harmonic distortion. The proposed modulation scheme achieves the same switching loss reduction and improved output performance by modifying the dwell time order. The proposed evenly clamped DPWM method was compared with the conventional clamped DPWM method through simulations and experiments.

Generalized Harmonic Control for CHB Converters With Unbalanced Cells Operation

Multilevel cascaded H-bridge (CHB) converters are an attractive solution for multiple applications like flexible ac transmission systems and solid-state smart transformers, among others. This article is focused on a CHB working with unbalanced conditions per cell (different cell dc voltages and/or cell voltage references). In this scenario, the phase-shifted pulsewidth modulation (PS-PWM) technique produces a harmonic distortion around twice the carrier frequency and its multiples in the CHB output voltage. In this article, a generalized variable-angle PS-PWM method is presented in order to mitigate this drawback improving the CHB output voltage harmonic spectrum. The proposed method is based on applying a mathematical search algorithm to determine the phase displacement angles to be applied to the PS-PWM technique. Experimental results show how this objective is achieved without introducing any disadvantage in the CHB operation. The method can be applied to CHB with any number of cells.

An Optimized Model Predictive Control for Three-Phase Four-Level Hybrid-Clamped Converters

An optimized model predictive control (MPC) method is proposed based on the selected switching states to control the four-level hybrid-clamped converter. The proposed method utilizes 64, instead of 512, switching states, compared with a conventional MPC, which greatly eases the calculation burden while achieving the high-quality regulation of output currents and the balance of capacitor voltages. The steady-state performance at both high and low frequencies is investigated, and results are compared with those by the traditional carrier phase-shifted pulsewidth modulation method. The dynamic response to the current or frequency step change is also evaluated. Both simulation and experimental results validate the feasibility and effectiveness of the optimized MPC method.

A Modified PSPWM for a Five-Level Hybrid-Clamped Inverter to Reduce Flying Capacitor Size

In order to reduce the size of high-voltage flying capacitors in a five-level hybrid-clamped inverter, a modified phase-shifted pulsewidth modulation (PWM) method is proposed in this paper. The four carrier waves are redistributed and the charge/discharge time of the high-voltage capacitor can be reduced. The only disadvantage of this PWM method is that the harmonic characteristic will become worse. However, no low-order harmonics is imported and most of the harmonics are around carrier frequency and multitimes the carrier frequency, which are very easy to be filtered. Simulation and experimental results are presented to demonstrate the effectiveness of this method.

CMV reduction for five‐level ANPC converter by PS‐PWM strategy

Five-level active neutral point clamped (ANPC) converter has become one of the most attractive topologies in industry applications, especially in the field of the motor drive. A novel common-mode voltage (CMV) reduction strategy for five-level ANPC is presented, which is based on the phase-shifted pulse-width modulation (PS-PWM). A basic PS-PWM method is presented, which can realise the NP voltage and the flying capacitor (FC) voltages balance. Moreover, a general CMV reduction method is summarised. The proposed CMV reduction strategy can minimise the CMV by injecting zero-sequence voltage to the modulation wave and it does not affect the ability of NP voltage and FC voltages balance. The validity of the proposed CMV reduction method based on PS-PWM strategy is verified by simulation.

Reduction of Common-Mode Voltage in Multiphase Two-Level Inverters Using SPWM With Phase-Shifted Carriers

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper.

Voltage Balancing Control of a Four-Level Hybrid-Clamped Converter Based on Zero-Sequence Voltage Injection Using Phase-Shifted PWM

Four-level hybrid-clamped (4L-HC) inverter is a newly proposed topology which is suitable for high-performance medium-voltage drives. Each phase of this topology consists of eight switches and a flying capacitor and the dc-link is split into three parts by two neutral points. In order to ensure the topology operating properly, the voltages across the flying capacitors and three dc-link capacitors should be controlled and maintain balanced at their nominal values. This paper presents a decoupled voltage balancing method for this 4L-HC inverter, including the voltage balancing of dc-link capacitors and flying capacitors. A modified phase-shifted pulse-width modulation method is used to regulate the voltages of flying capacitors and the central dc-link capacitor. The relationship between the neutral-point currents and the output voltage is studied and the upper and lower dc-link capacitor voltages are balanced by injecting an optimum zero-sequence voltage. Simulation and experimental results are presented to verify the validity of this method.

Reducing the stroboscopic effects of LED luminaires with pulse width modulation control

Pulse width modulation for dimming the light output of LEDs has become common. When pulse width modulation is used at low frequencies unwanted visual artefacts including flicker perception and stroboscopic effects may occur. These artefacts need to be avoided or at least reduced to a minimum in order to obtain high user acceptance. In this paper, an optimized phase-shifted pulse width modulation method is described, implemented and validated in a visual experiment. The method is intended to minimize the stroboscopic effect on a reference surface by first optimizing the LED units of a single LED luminaire and then co-optimizing several of these luminaires. The optimized pulse width modulation waveforms are then compared to standard pulse width modulation dimming methods. In the visual experiment, 13 subjects rated the extent of the stroboscopic effect of standard and optimized waveforms in a white painted experimental room. The results indicate that the optimized waveforms are indistinguishable from constant light.

Phase-shifted Discontinuous Pulse-Width Modulation Methods for Multi-level Inverters Operated in Over-modulation Range

This article presents combinations of the generic phase-shifted pulse-width modulation method with conventional discontinuous pulse-width modulation methods operated in the over-modulation range. The treated discontinuous methods are the third harmonic injection, Depenbrock's DPWM1, and Ogasawara's DPWM2. The significant advantage of the present approach over the conventional phase disposition pulse-width modulation method is the equal power flow between the H-bridges and the improved distribution of the switching operations number between them. Furthermore, they provide improved linearity in the over-modulation range. The proposed pulse-width modulation methods are analyzed by extensive simulation results. Several aspects, such as the total harmonic distortion factor of the inverter output currents and voltages, harmonic content, frequency spectrum distribution, and switchings number, are studied.

New mixture of hybrid stacked multicell with half‐cascaded converter to increase voltage levels

This study presents a new topology of hybrid stacked multicell (SM) converter which generates high number of output voltage levels with fewer number of power electronic switches. The proposed topology is composed of three parts including traditional SM converter, half-cascaded converter and H-bridge converter. In other words, this converter is the mixture of H-bridge converter and SM converter series with half-cascaded converter. Number of output voltage levels and the rootmean- square value in proposed converter is four times than that of traditional flying capacitor multicell and SM converters. Moreover, it improves output voltage frequency spectrum and decreases the number and rating of components, stored energy and rating of flying capacitors which are available in the proposed converter. For switching this converter, phase-shifted pulse-width modulation method has been used. Therefore the self-balancing trait of the flying capacitor converter is preserved in presented converter. The suggested topology is simulated using MATLAB/SIMULINK software, and simulation results are presented to indicate the well-performance of the novel converter. In addition, the experimental results of proposed topology prototype have been presented to validate its practicability.

Carrier‐based pulse‐width modulation techniques for asymmetrical six‐phase open‐end winding drives

The study discusses development, implementation and performance of carrier-based pulse-width modulation (PWM) techniques for an asymmetrical six-phase open-end winding drive supplied by two two-level six-phase voltage source inverters (VSIs). The VSIs are fed from two equal and mutually isolated dc voltage sources, so that the same performance as with a three-level VSI in single-sided supply mode can be achieved. The considered modulation techniques are the in-phase disposition (PD-PWM) and the alternate phase opposition disposition, which are both classified as level-shifted PWM methods, and the phase-shifted PWM method. The performance is studied and compared using computer simulations and experiments undertaken on a laboratory prototype. It is shown that, in contrast to the three-phase and five-phase cases, the PD-PWM method does not offer the best performance.

Improved Natural Balancing With Modified Phase-Shifted PWM for Single-Leg Five-Level Flying-Capacitor Converters

Flying-capacitor converters (FCCs), like most multilevel converter topologies, require a balancing mechanism of the capacitor voltages. FCCs feature natural voltage balancing when a special modulation technique is used. The classic methods, such as phase-shifted pulse width modulation (PS-PWM), result in very slow balancing for some duty-ratio ranges. Previous work has shown that for a single-leg five-level FCC, one time constant is infinite for a zero desired output voltage. In this paper, a modified PS-PWM scheme for a single-leg five-level FCC is presented, which results in faster balancing over the total duty-ratio range. The modified PS-PWM scheme is studied, resulting in an averaged voltage-balancing model. This model is verified using simulations and experiments. The modified PS-PWM scheme solves the slow-balancing problems of the normal PS-PWM method for odd-level FCCs, while maintaining the passive control property, and it provides a self-precharge capability.

Transistor-Clamped H-Bridge Based Cascaded Multilevel Inverter with New Method of Capacitor Voltage Balancing

This paper presents a three-phase cascaded multilevel inverter that uses five-level transistor-clamped H-bridge power cells. Multicarrier phase-shifted pulse-width modulation method is used to achieve balanced power distribution among the power cells. A new method to balance the midpoint capacitor voltage in each cell is developed and tested. The analysis of the output voltage harmonics and the total power losses covering the conduction and the switching power losses are carried out and compared with the cascaded neutral-point-clamped and the conventional cascaded H-bridge inverters. For verifications, the proposed inverter is experimentally tested on an induction motor. From the results, the proposed inverter provides higher output quality with relatively lower power loss as compared to the other conventional inverters with the same output quality.