Measured Phase Noise Research Articles

Frequency-Modulated Continuous-Wave Chirp Frequency Error and Phase Noise Measurement: How to Characterize Frequency-Modulated Continuous-Wave Chirp Using Commercial Oscilloscope

Frequency-Modulated Continuous-Wave Chirp Frequency Error and Phase Noise Measurement: How to Characterize Frequency-Modulated Continuous-Wave Chirp Using Commercial Oscilloscope

Post-Fabrication Performance and Longevity Improvement of a Phase-Locked Loop With an On-Chip Phase Noise Measurement Circuit

Post-Fabrication Performance and Longevity Improvement of a Phase-Locked Loop With an On-Chip Phase Noise Measurement Circuit

A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS

With a 65-nm CMOS process, a V-band wideband injection locking (IL) frequency tripler is proposed by cascading a multiplier and a driver amplifier stage. Concerning high output power and efficiency performance over a wideband locking range (LR), two transformer-based IL topologies are analyzed in the multiplier and driver stages, in which the cross-coupled pair is connected at the input and output ports of the transformer, respectively. Moreover, the active device is carefully designed in terms of the operating point of the harmonic generator and device sizing in the driver amplifier stage. With measurements, the proposed tripler achieves a maximum measured output power of 7.3 dBm with 22.4% output-to-DC power efficiency and 26.8% LR from 50.4 to 66 GHz. Including the output driver amplifier, the IL tripler consumes 24 mW DC power. The measured fundamental and 2nd-harmonic rejection ratios (HRR) are both better than 30 dBc, while the measured phase noise (PN) degradation is in close agreement with the theoretical value.

Robust laser phase noise measurement by integration heterodyne for coherent beam combining applications

Phase noise characteristics are critical for coherent beam combination engineering. Heterodyne with integration method for phase noise measurement has been studied numerically and experimentally, which reveals that the method is not only simple to implement with the least equipment but also capable of phase retrieval using under-sampling data. The integration method is compared with the traditional low-pass filter (LPF) method from both numerical and experimental perspectives. By introducing an evaluation criterion of measurement accuracy, the errors of the integration method are 0.44% and 0.08% for white noise and pink noise cases, respectively, which are smaller than that achieved by LPF one (1.52% and 0.25%). The errors of the integration method are below 1.4% when under-sampling data has been employed, which means that large consumption of data processing can be avoided, and the method is robust. Phase noise measurements in quiet laboratory and disturbed conditions are implemented, and the error between the results of the sampling rate of 250 MHz and 31.25 MHz is less than 0.08%, which is consistent with the simulation and demonstrates the excellent performance of the integration method.

Design and simulation of a tunable parity-time symmetric optoelectronic oscillator utilizing integrated components

Non-Hermitian photonics, relaying on parity-time (PT) symmetry, have shown promise in achieving mode selection for optical or microwave single-mode oscillation. Typically, a PT-symmetric system is constructed using two coupled loops with identical geometry. This article utilizes the PT-symmetry property to select a single frequency mode in an optoelectronic oscillator (OEO). However, traditional OEO implementations often involve discrete components, limiting widespread adoption due to factors such as size, weight, power consumption, and cost. Our aim in this paper is to leverage integrated components within the OEO loop. The proposed structure incorporates an integrated micro-ring resonator (MRR) with a high-quality factor (Q-factor) that serves both as a modulator and a resonator. Additionally, we suggest employing an adjustable integrated power splitter utilizing a micro heater to balance the gain and loss of two mutually coupled OEO loops. In this configuration, two integrated photo detectors (PD) are also utilized. In this setup, the single-frequency mode can be easily identified by simultaneously utilizing the properties of PT-symmetry and an integrated high-Q-factor resonator, obviating the need for a narrowband microwave filter. By adjusting the center frequency of the microwave photonic filter (MPF), the frequency of the generated signal can be tuned over a wide range. For instance, setting the generated frequency of the microwave signal to 11.5 GHz results in a measured phase noise of − 76.5 dBc/Hz at a 10-kHz offset frequency, with a side mode suppression ratio (SMSR) of 40 dB.

DAC phase and amplitude noise experimental studies in RZ, NRZ and RF modes

Amplitude and duration of pulses generated by current cells of multimode DAC may differ in real DACs. In this case the problem arises of current pulse parameters defining, their relationship with frequency domain response and noise parameters of DAC, which can be experimentally determined. The article describes the measurements of frequency domain response, phase noise and amplitude noise of multimode DAC output signal in RZ, NRZ and RF (mixed) mode. Phase noise and amplitude noise of multimode DAC in RZ and RF modes calculation uses experimental data obtained in RZ mode. Measurement and consequent calculation of AD9739 DAC phase and amplitude noise confirmed the theoretical analysis.

A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A frequency servo system-on-chip (FS-SoC) featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium (Cs) atomic clocks. The proposed power stabilization loop (PSL) technique, incorporating an off-chip power detector (PD), ensures that the output power of the FS-SoC remains stable, mitigating the impact of power fluctuations on the atomic clock's stability. Additionally, a one-pulse-per-second (1PPS) is employed to synchronize the clock with GPS. Fabricated using 65 nm CMOS technology, the measured phase noise of the FS-SoC stands at −69.5 dBc/Hz@100 Hz offset and −83.9 dBc/Hz@1 kHz offset, accompanied by a power dissipation of 19.7 mW. The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7 × 10−11 with 1-s averaging time.

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology

In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

A low-power single-core 24.5-to-29.1 GHz CMOS LC voltage-controlled oscillator (VCO) is presented. The proposed VCO uses an innovative differential cross-coupled architecture in which an additional pair is connected to the main pair to increase the effective transconductance, resulting in lower power consumption and reduced phase noise (PN). The proposed VCO is fabricated in a 1P9M standard CMOS process and sustains oscillation at 29.14 GHz with power consumption as low as 455 μW (650 μA from a 0.7 V supply), which is ~20% lower than a conventional CMOS LC VCO without Gm-enhanced differential pairs built through the same process (700 μA from 0.8 V supply). When consuming 880 μW (1.1 mA from 0.8 V), the proposed VCO exhibits a tuning range of 4.6 GHz (from 24.5 GHz to 29.1 GHz). Moreover, it exhibits a measured phase noise (PN) better than −106.5 dBc/Hz @ 1 MHz and −132.0 dBc/Hz @ 10 MHz, with figure-of-merit (FoM) results of 195.2 dBc/Hz and 200.3 dBc/Hz, respectively.

Residual phase noise measurements of elements of the radio frequency path of radiometric receivers

In this work, the measurement of the residual phase noise of amplifiers and frequency multipliers using frequency doublers and step recovery diodes, were performed utilizing the interferometric method. The results obtained showed the possibility of using the interferometric method in measuring the phase noise of radio frequency paths of radiometric receivers. The measured values of residual phase noise can be used to evaluate the characteristics of the radio frequency paths of receivers.

Phase noise of signal generators with multichannel digital synthesizers

Wide use of a direct digital synthesizer (DDS) and digital to analog converters (DAC) in digital antenna arrays permits for fast modulation parameters variations and beam positioning, and also improves the quality of beam forming due to high accuracy of signal generation. However, any systematic and random phase deviations of array channels not only lead to distortion of radiation pattern but also cause deterioration of signal processing at receiver end. Phase noise is one of critical parameters of such systems. Traditional theory and empirical methods assumes small or zero phase deviation of phase of channel output signal when combining these signals. We have proposed the model in which coupling of AM and PM noise persists for any arbitrary phase deviation of channels in multistage circuits comprising multichannel digital synthesizers. Absolute phase noise measurements of combined DACs outputs for zero phase offset and antiphase modes with two values of DAC output signal amplitude difference permit for estimation of residual phase noise of DAC and clock receiving and distribution circuitry and demonstrate good compliance of results of calculation.

A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz

This work presents a novel trusted LC voltage-controlled oscillator (VCO) with an embedded compact analog Physically Unclonable Function (PUF) used for authentication. The trusted VCO is implemented in a 1P9M 65 nm standard CMOS process and consumes 1.75 mW. It exhibits a measured phase noise (PN) of −104.8 dBc/Hz @ 1 MHz and −132.2 dBc/Hz @ 10 MHz offset, resulting in Figures of Merit (FoMs) of 191.7 dBc/Hz and 199.1 dBc/Hz, respectively. With the measured frequency tuning range (TR) of ~5.5 GHz, the FoM with tuning (FoMT) reaches 197.6 dBc/Hz and 205.0 dBc/Hz at 1 MHz and 10 MHz offset, respectively. The analog PUF consists of CMOS cross-coupled pairs in the main VCO to change analog characteristics. Benefiting from the impedance change and parasitic capacitance of the cross-coupled pairs, the AC and DC responses of the VCO are utilized for multiple responses for each input. The PUF consumes 0.83 pJ/bit when operating at 1.5 Gbps. The proposed PUF exhibits a measured Inter-Hamming Distance (HD) of 0.5058b and 0.4978b, with Intra-HD reaching 0.0055b and 0.0053b for the current consumption and fosc, respectively. The autocorrelation function (ACF) of 0.0111 and 0.0110 is obtained for the current consumption and fosc, respectively, at a 95% confidence level.

Broadband phase noise measurement of single-frequency lasers by the short-fiber recirculating delayed self-heterodyne method.

Characterization of single-frequency lasers (SFLs) requires a precise measurement of their phase noise. However, there exists a contradiction between the frequency range and laser phase noise measurement sensitivity in the delay self-heterodyne method. Achieving a broadband and highly sensitive phase noise measurement often requires overlapping the results obtained from different delay lengths. In this study, we present a precisely designed short-fiber recirculating delayed self-heterodyne (SF-RDSH) method that enables the broadband and highly sensitive laser phase noise measurement in a compact setup. By designing the length of the delay fiber based on a theoretical model, the RDSH technique with a shortest delay length of 200 m enables a highly sensitive laser phase noise measurement from 1 Hz to 1 MHz for the first time, to our knowledge. In the experiment, we demonstrate the broadband phase noise measurement of an SFL by analyzing the 1st and 10th beat notes.

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

Application of Machine Vision Technology in Defect Detection of High Performance Phase Noise Measurement Chips

Application of Machine Vision Technology in Defect Detection of High Performance Phase Noise Measurement Chips

Laser Heterodyne Detection Based on Photon Time–Domain Differential Detection Avoiding the Effect of Decoherence Phase Noise

Laser heterodyne detection (LHD) is a key velocimetry technique that provides better accuracy and sensitivity than direct laser detection. However, random phase noise can be introduced by the surface topography of the moving target undulation or atmospheric turbulence during transmission. The random phase noise causes the target echo to undergo decoherence, resulting in degradation of the signal-to-noise ratio (SNR). Here, we propose a novel LHD method based on photon time–domain differential detection. It can infer the heterodyne spectrum of the target echo and the local oscillator light from the time intervals of the photon arrival. The time interval statistic is a relative quantity, which can effectively avoid the effect of random phase noise in LHD. With our method, the SNR of LHD can be improved in application scenarios where the target echo is decoherent. We developed a complete solution model for acquiring the heterodyne spectrum based on photon time–domain differential detection and performed proof-of-principle experiments. The experimental results show that in the presence of random phase noise, the SNR and velocity measurement error of our method are significantly better than that of the conventional method, and the larger the phase noise is, the more the SNR and velocity measurement error of our method are improved. Moreover, along with the increase in phase noise, the SNR of our method is basically unchanged, which also indicates that our method is not affected by random phase noise. This advantage is significant for photon-level weak echoes that require long detection times to be detected.

Wrapped phase aberration compensation using deep learning in digital holographic microscopy

In digital holographic microscopy (DHM), phase aberration compensation is a general problem for improving the accuracy of quantitative phase measurement. Current phase aberration compensation methods mainly focus on the continuous phase map after performing the phase filtering and unwrapping to the wrapped phase map. However, for the wrapped phase map, when larger phase aberrations make the fringes too dense or make the noise frequency features indistinct, either spatial-domain or frequency-domain based filtering methods might be less effective, resulting in phase unwrapping anomalies and inaccurate aberration compensation. In order to solve this problem, we propose and design a strategy to advance the phase aberration compensation to the wrapped phase map with deep learning. As the phase aberration in DHM can be characterized by the Zernike coefficients, CNN (Convolutional Neural Network) is trained by using massive simulated wrapped phase maps as network inputs and their corresponding Zernike coefficients as labels. Then the trained CNN is used to directly extract the Zernike coefficients and compensate the phase aberration of the wrapped phase before phase filtering and unwrapping. The simulation results of different phase aberrations and noise levels and measurement results of MEMS chip and biological tissue samples show that, compared with current algorithms that perform phase aberration compensation after phase unwrapping, the proposed method can extract the Zernike coefficients more accurately, improve the phase data quality of the consequent phase filtering greatly, and achieve more accurate and reliable sample profile reconstruction. This phase aberration compensation strategy for the wrapped phase will have great potential in the applications of DHM quantitative phase imaging.

Simple, low-cost, and well-performing optical phase-locked loop for frequency and phase locking of semiconductor lasers.

We demonstrate a simple, low-cost, and well-performing optical phase-locked loop (OPLL) circuit with ADF4007 as the phase frequency detector chip to achieve frequency and phase locking of two semiconductor lasers in both short and long terms. The measured short term performances, determined by fast feedback, show that the spectral width of the beat signal is low, around 1Hz, and the residual phasing error is 0.04r a d 2. The measured long term performances, determined by slow feedback, show that the drift of the central frequency of the beat signal is within 1.1(1)Hz in 2h, and the derived Allan deviation is less than 0.4Hz within all integration times of up to 1000s. The phase noise measurement shows a suppression of phase noise of the beat signal from free running to closed-loop OPLLs in a Fourier frequency of 10Hz-20kHz. These measurements show that the OPLL circuit we modified can fit most scientific experiments requiring a fixed frequency difference and phase coherence.

A High FoM and Low Phase Noise Edge-Injection-Based Ring Oscillator in 350 nm CMOS for Sub-GHz ADPLL Applications

This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 dBc/Hz. The core area of this edge-injection-based DRCO is only 0.08 mm2.