Phase-locked Loop In Presence Research Articles

RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer

Frequency Synthesizer forms the heart of electronic communication system. Phase Locked Loop (PLL) based Frequency Synthesizers over the years has become the ubiquitous solution for generation of stable clock source. But it is a challenging task to design and develop PLL to be used in radiation environment such as in satellites, space systems and military electronics. Since impact of radiation strike on PLL is said to introduce transient faults resulting in increased timing jitter, distortion in phase, and bit flips. One or more of the above said effects can initiate false triggering which may result in incorrect data to be latched, loss of synchronization in data processing and networking. This may lead to catastrophic effect. Hence, as the stability of frequency synthesizer is of vital importance, there is a stressful need for design of radiation hard, fault tolerant frequency synthesizer. With this motivation, in this paper, a radiation hard CMOS Charge Pump PLL is designed to synthesize a 2.4GHz frequency source using 20MHz reference input frequency. The proposed radiation hard PLL design uses a hybrid Radiation Hardening By Design (RHBD) fault tolerant technique combined with redundancy, hence offering a twofold level of fortification from radiation spikes. Cadence tool was used for simulation. The PLL designed has exhibited satisfactory performance. The RHBD Charge Pump PLL in presence of radiation strike resulted in rms jitter of 128.9ps, phase noise of -94.03dbc/Hz and settling time of 159ns against the IEEE 802.11b/g standard requirement of 250ps jitter, -110dbc/Hz phase noise and 10us setting time.

Chaos from second-order PLL in presence of CW interference

The chaotic behaviour of a second-order phaselocked loop (PLL) in the presence of continuous wave (CW) interference is examined. The Lyapunov exponents and dimension of the system are calculated to confirm the chaotic phenomenon. A range of interfering signal power and frequency has been found where chaos could occur.

An Optical Heterodyne PSK Receiver using an Improved Decision Directed PLL in Presence of Adjacent Channel Interference

An optical phase-shift-keying (PSK) heterodyne receiver using synchronous detection by means of a decision directed phase locked loop (PLL) has been investigated taking the effect of shot noise, phase noise, adjacent channel interference and loop propagation delay. The evaluation of phase-error variance and error probability calculations are performed without affecting the loop stability. The plots of error probability with PNB are presented as a function of normalised optical domain channel spacing for several linewidth-to-bit-rate ratios. A relative improvement in error probability of 4 dB has been obtained with normalised control parameter of 0.4, D = 10Rb & δf = 0.001Rb.