Phase-locked Loop Based Frequency Synthesizer Research Articles

Синтезатор дискретной сетки частот на основе антиферромагнитного спинтронного осциллятора

Dynamics of an antiferromagnetic spintronic oscillator phase-locked loop-based frequency synthesizer, which generates terahertz oscillations in a wide frequency range under the influence of direct current, was investigated. By the method of slowly varying amplitudes, a dependence of the gain on the ring of the phase locked loop on the difference in frequencies of synchronized oscillations at different division coefficients in the feedback circuit is obtained. It is shown that as the division coefficient increases, the band of synchronized oscillations decreases with unchanged parameters of the antiferromagnet-based spintronic oscillator.

Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

Noise and process variation present a practical limit on the performance of analog circuits. This paper proposes a methodology for modeling and verification of analog designs in the presence of shot noise, thermal noise, and process variations. The idea is to use stochastic differential equations to model noise in additive and multiplicative form and then combine process variation due to 0.18 μm technology in a statistical run-time verification environment. The efficiency of Monte-Carlo and Bootstrap statistical techniques are compared for a Colpitts oscillator and a phase locked loop-based frequency synthesizer circuit.

Frequency Synthesizer With Dual Loop Frequency and Gain Calibration

A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 μm CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain ( KVCO of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 μs including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is -123 dBc/Hz and the integrated phase error (1 kHz-2 MHz) is 1.26 °.

A fast lock frequency synthesizer using an improved adaptive frequency calibration

An improved adaptive frequency calibration (AFC) has been employed to implement a fast lock phase-locked loop based frequency synthesizer in a 0.18 μm CMOS process. The AFC can work in two modes: the frequency calibration mode and the store/load mode. In the frequency calibration mode, a novel frequency-detector is used to reduce the frequency calibration time to 16 μs typically. In the store/load mode, the AFC makes the voltage-controlled oscillator (VCO) return to the calibrated frequency in about 1 μs by loading the calibration result stored after the frequency calibration. The experimental results show that the VCO tuning frequency range is about 620–920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is −82 dBc/Hz. The lock time is about 20 μs in frequency calibration mode and about 5 μs in store/load mode. The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.