Phase-locked Loop Applications Research Articles

Phase-Locked Loop Applications Under Weak Grid Conditions Assisted with Dual-Layer Filtering

Phase-Locked Loop Applications Under Weak Grid Conditions Assisted with Dual-Layer Filtering

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application

Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application

An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated.

180 nm NMOS voltage-controlled oscillator for phase-locked loop applications

<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.</p>

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

This article introduces a novel approach of hybrid current-starved ring voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications. In this, two novel VCO designs are proposed. The first design is the current starved pull-up sleepy ring VCO which offers improved frequency of oscillation and reduced phase noise. The second design utilizes a hybrid current starved ring VCO with the bulk-driven keeper technique which yields better results by reducing the power consumption and mitigating leakage current. The proposed circuit is analysed with various process corners and performs parametric analysis and Monte-Carlo analysis to verify the robustness of the circuit using Cadence Virtuoso tool with 45 nm gpdk library. The average power of the proposed −2 circuit is 7.38 µW, and it achieves an oscillation frequency of 6.965 GHz at 1 V supply. It has low phase noise of −121.49dBc/Hz at 1 MHz, and the output noise of −166.42 dB. The obtained figure of merit (FOM) is −185.95dBc/Hz. The proposed design exhibits a frequency tuning range of 92.8 %. The results clearly demonstrate that the proposed design is extremely tolerant to PVT (process, voltage, and temperature) variations making it well suitable for high-frequency PLL applications.

Dynamic stability improvement scheme for dual-sequence PLLs in VSC based renewable energy generation system during asymmetrical LVRT

This paper studies the influence introduced by the application of dual-sequence phase-locked loops (PLLs) structure for dynamic stability of the voltage source converter (VSC)–based renewable energy generation system (REGS) during asymmetrical low voltage ride through (LVRT) in the weak grid. The result unveils that applying the dual-sequence PLLs structure will increase the numbers of modals with weak damping and changes the unstable modal during the asymmetrical LVRT, compared with the single-sequence PLL structure, because it brings novel and complex dynamic interactions. Hence, the analyzed stability conclusions and designed improved control strategies for the system with single-sequence PLL structure during asymmetrical faults are not applicable to grid-connected systems using the dual-sequence PLLs. This article investigates the fundamental cause of small-signal instability for VSC during asymmetrical LVRT caused by the dual-sequence PLLs. In addition, the influence of current control loops (CCLs) control parameters on the dynamic performance of dual-sequence PLLs is analyzed. Finally, an improved control scheme is designed to improve the dynamic stability of the system adopted dual-sequence PLLs during asymmetrical LVRT. The validations are carried out in simulations and experiments to prove the proposed schemes’ effectiveness.

Sleepy Stack CSVCO with wide tuning and low power for PLL applications

This paper describes the implementation of low power leakage technique called Sleep-Stack in a Current Starved Voltage Controlled Oscillator (VCO) a block of Phase Locked Loop (PLL). The VCO is a electronic oscillator, whose oscillation frequency is decided by the control voltage. The major issue in the VCO is the power consumption, which has an impact on the performance of the PLL. The VCO that limits the current is preferred than the other oscillator which is called as Current Starved VCO. The work i.e. the design of Current Starved VCO is implemented using low power leakage technique called Sleepy Stack. This has been implemented in 45nm CMOS Technology with a supply voltage of 1.2 V in Cadence Software. The parameters like average power, oscillation frequency, and delay are calculated for this technique. The corner analysis has been performed for all this technique to verify the stable/linearity even in the worst case scenario. It has been observed that the sleepy stack technique with gain 23.99 GHz/V, phase noise -63.8dBc/Hz, Figure of Merit value of -142.234dBc/Hz and having frequency tuning range of 77.79%.The average power obtained for the Sleepy Stack technique is 11.88nW which is less than that of the existing CSVCO.

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Influence of the Phase-Locked Loop on the Design of Microgrids Formed by Diesel Generators and Grid-Forming Converters

In recent years, microgrids (MGs) with renewable energy sources, diesel gen-sets, and droop-controlled converters have been increasingly used to guarantee the continuity of power supply in remote areas. Renewable energy sources have been typically connected to MGs by using an electronic converter that features the two controllers: a current-control loop and a phase-locked loop (PLL). Stability issues related to the PLLs application in electrical grids have already been addressed in the literature; however, dynamic interactions in MGs caused by PLLs have not been sufficiently explored. In this article, an MG that includes a grid-feeding voltage source converter and a grid-forming device (diesel gen-set or converter) is studied. All network elements are modeled analytically and the eigenvalue and participation-factor analyses are used to analyze the interactions between the devices. It is demonstrated that MGs formed by diesel gen-sets have reduced stability limits. Also, it is shown that stability margins of MGs formed by droop-controlled converters can be improved by changing the control parameters (e.g., PLL and internal controllers bandwidths). The main findings and conclusions are summarized and presented as a practical MG design guide. Theoretical results are validated in a lab environment comprising two 15 kW converters and one 75 kW grid emulator.

An improved parasitism predation algorithm for frequency regulation of a virtual inertia control based AC microgrid

ABSTRACT Frequency stability is one of the major challenges in renewable energy source-based microgrids. This issue can be resolved by employing virtual inertia control that helps in improving damping properties and stability. In applying this control method, a phase-locked loop (PLL) is used to acquire the assessment of the frequency data of the microgrid. Nonetheless, the application of PLL in microgrids produces larger frequency oscillation due to its system dynamics. To solve such issues, we propose a robust Interval Type-2 Fuzzy Logic PID Controller (IT2FPID) for the virtual inertia control to limit the unwanted frequency measurement impacts while simultaneously improving the microgrid system stability. Further, a novel improved parasitism predation algorithm (IPPA) algorithm is proposed to tune the controller parameters. The performance of our proposed solutions is studied by comparing the simulation results with a few standard techniques considering the change in system parameters and different paces of renewable energy source penetration.

A bipolar offset binary time-to-digital converter using time amplifiers based on time-to-current compensation

A bipolar low-power pipeline time-to-digital converter (TDC) for digital phase-locked loop (DPLL) applications is implemented with six 1-bit cascaded stages. The stages consist of a compensated ×2 time amplifier (TA) using the time-to-current conversion technique, two modified SR-latch-based time comparators, and a static logic called offset-64, which aligns the output bit of the stage to create a 7-bit output code without the zero-gain issue. The presented mathematical analyses reveal the low sensitivity of the proposed TDC to the offset of the TA. The layout of the proposed TDC was designed in a 65 nm CMOS technology. Post-layout simulation results demonstrate a 1.7 ps time resolution and power consumption of 450 μW for a sampling frequency of 125 MS/s.

A dynamic current mode design approach of 2/3 prescaler for phase locked loop application

A dynamic current mode design approach of 2/3 prescaler for phase locked loop application

Performance improvement of PMSM rotor position estimation by using adaptive hybrid filter based PLL

To achieve a satisfactory sensorless control performance of permanent magnetic synchronous machine (PMSM), an effective rotor position estimation method is a critical factor. As a useful tool for phase estimation technique, there exists extensive application of phase-locked loops (PLLs) in this task. Nevertheless, since harmonics are existed in the back electromotive force (EMF), the accuracy of position estimation method based on PLL is still low. In this paper, an adaptive hybrid filter based PLL is proposed to enhance the estimation performance. The proposed adaptive hybrid filter is frequency-adaptive, which means the performance is not affected under varying-speed operating conditions. Moreover, all the harmonic disturbances can be totally eliminated. The proposed method is validated under simulation. The results confirm the effectiveness of the proposed method.

A Flexible Digitally Controlled Oscillator Structure to Reconfigure the Frequency Band in Multi-band RF AD-PLL System

Reconfigurable architectures are more prominent in modern-day multi-band radio systems. This work has been conceptualized for a flexible 8-bit digitally controlled oscillator (DCO) design to suit reconfigurable RF all-digital phase-locked loop applications. To efficiently utilize the area, power consumption and attend to several operating frequencies, an optimal design of LC-tank based DCO topology with both L and C components contributing to the coarse and fine-tuning of the DCO’s frequency of oscillation has been proposed. The design has been carried out in the Cadence Spectre RF tool with UMC180 nm technology. The proposed 8-bit DCO exhibits wide bandwidth, generating 240 oscillating frequencies in the LTE frequency band and occupies less area of 70 × 18 µm. The frequency of oscillation varies from 491.5 MHz to 3.392 GHz designed for an 8-bit digital control word with a tuning range percentage of 149%. The maximum phase noise obtained is −103.57 dBc/Hz @ 10 MHz offset causing a figure of merit (FOM) of −144.167 dBc/Hz. The total power consumed by the DCO ranges from 1.05 to 9.5 mW approximately.

Design and analysis of radiation-tolerant high frequency voltage controlled oscillator for PLL applications

Single Event Transients (SET’s) occur in analog integrated circuits due to the strike of a heavy-ion (or) heavy energy proton at the transistor junction. It produces electron–hole pairs, which propagates in the circuit and results in amplitude variation, phase displacement at the output voltage. This paper presents a Radiation Hardened By Design (RHBD) current starved inverter buffer Voltage Control Oscillator (VCO) for the application of Phase Locked Loop (PLL). The proposed VCO is composed of current starved inverter delay VCO and majority voter. The current starved inverter delay VCO is designed with the inverter delay cell, and a single current source is shared for each delay cell. The majority voter is designed by Gate Diffusion Input (GDI) logic to reduce power consumption. The Linear Energy Transfer (LET) ranging from 14.47 to 100 Mev−cm2∕mg is applied at the nodes of VCO. The proposed mitigation technique reduces the SET effect by 98%, and it operates at the frequency range from 0.5 GHz to 2.5 GHz with the power consumption of 290 μW.

Application of phase locked loops in current and voltage discriminating elements of microprocessor-based relay protection devices

Application of phase locked loops in current and voltage discriminating elements of microprocessor-based relay protection devices

Three-phase phase-locked loop algorithm and application to a static synchronous compensator

This work presents a phase-locked loop (PLL) algorithm for the detection of positive-sequence and negative-sequence grid voltages in three-phase systems. Since it employs an adaptive filter (AF), it is possible to track the fundamental component of the grid voltages accurately even in the presence of harmonics, subharmonics, and interharmonics. This aspect is of major concern for practical applications, especially because some popular algorithms present limited performance in such scenarios, e.g., the decoupled double synchronous reference frame PLL (DDSRF-PLL) and double second-order generalized integrator frequency-locked loop (DSOGI-FLL). A thorough comparison among the proposed method and other similar structures is presented in terms of steady-state and dynamic behaviors to show that the introduced PLL presents high immunity to power quality disturbances. Unfortunately, a possible drawback lies in the slow dynamic response due to the AF. In order to verify the applicability of the proposed approach, it is also incorporated to the control structure of a grid-connected power converter operating as a static synchronous compensator (STATCOM). This converter aims at regulating the ac voltage at the point of common coupling (PCC) and power factor correction. A detailed mathematical analysis is presented and experimental results are also discussed to validate the theoretical assumptions.

Design and Analysis of Low Power and High Frequency Current Starved Sleep Voltage Controlled Oscillator for Phase Locked Loop Application

This paper presents a current starved sleep voltage-controlled oscillator(VCO) for the Phase Locked Loop (PLL) at high frequency with low power. The PLL’s significance is still vital in many communication systems today, such as GPS system, clock data recovery, satellite communication, and frequency synthesizer. The PLL design for low voltage applications has many challenges, such as leakage power, supply voltage fluctuations. The VCO is an electronic oscillator which produces oscillating frequency for the control voltage. Current starved VCO is popular among the oscillators because it offers the right balance between low area, wide tuning range. VCO’s power consumption is most significant and has an impact on the performance of the low power PLL. This work proposes the many inverter delay techniques (stack delay cell, sleepy stack delay cell, sleep delay cell) techniques in current starved VCO, resulting in reduced leakage power consumption. Introducing the sleep transistor between the pull-up MOSFET and supply voltage in an inverter induces a reverse bias, causing the reduction in sub-threshold leakage current when both are in off condition. The current starved sleep VCO has been designed using CMOS 90nm technology and investigated at the operating frequency of 1 GHz and wide tuning range from 0.5GHz-5.8GHz. It is to be observed that the power dissipation of the VCO is 8.12μ W, which is 2.3X lesser to the conventional VCO, the phase noise of -115dBc/Hz @1MHz and figure of merit value of -228.2dBc/Hz.