Phase Interpolation Technique Research Articles

Simplification of Linear Beam-Forming Networks by Applying a Novel Phase Interpolation Technique

Simplification of Linear Beam-Forming Networks by Applying a Novel Phase Interpolation Technique

Analysis of Timing Accuracy and Sensitivity in a RF Correlation-Based Impulse Radio Receiver With Phase Interpolation for Data Synchronization

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level.

Phase singularity detection through phase map interpolation: Theory, advantages and limitations

BackgroundDuring a cardiac arrhythmia, reentrant waves rotate around critical points called phase singularities (PS). PS detection is relevant to the quantitative description of the dynamics and to the identification of potential targets for ablation. Phase interpolation techniques have been proposed to increase the accuracy of PS localization. Our aim is to provide a theoretical basis and a comparative analysis of these methods. MethodDifferent electrode configurations representing mapping systems or catheter multi-electrode arrays were considered: triangular mesh, regular square grid and circular arrays. Linear, spline and inverse squared distance interpolation were used to create a continuous map from discrete measurements of phase. Synthetic phase maps with a PS and background noise were generated. Monte-Carlo simulations were run over millions of realizations to estimate PS locations and calculate the false negative and false positive rates as a function of noise variance. ResultsLinear interpolation is shown to be exactly equivalent to the standard discrete approach without interpolation. Spline interpolation had lower false negative rate at the expense of a higher false positive rate in the presence of noise. Inverse squared distance interpolation reduced false positives and was more robust to noise but was more likely to fail to detect a PS. Phase interpolation decreased PS localization error down to 0.17 interelectrode distance. The error was largest when the PS was near an electrode. ConclusionPhase interpolation methods offer additional flexibility to find the adequate trade-off between reducing false positives and false negatives.

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $ . The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.

A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration

A first-order time-based ΔΣ modulator using voltage-controlled oscillator (VCO) is presented. The proposed modulator employs phase interpolation technique to enhance the time resolution of the VCO and digital calibration to improve the linearity of the VCO tuning curve. The proposed modulator, implemented in 0.13 μm CMOS process, achieves 55 dB peak signal-to-noise ratio and 52.5 dB peak signal-to-noise-and-distortion ratio at 600 MHz sampling frequency for 20 MHz input bandwidth and consumes 14.3 mW.

Parametric study of EEG sensitivity to phase noise during face processing

BackgroundThe present paper examines the visual processing speed of complex objects, here faces, by mapping the relationship between object physical properties and single-trial brain responses. Measuring visual processing speed is challenging because uncontrolled physical differences that co-vary with object categories might affect brain measurements, thus biasing our speed estimates. Recently, we demonstrated that early event-related potential (ERP) differences between faces and objects are preserved even when images differ only in phase information, and amplitude spectra are equated across image categories. Here, we use a parametric design to study how early ERP to faces are shaped by phase information. Subjects performed a two-alternative force choice discrimination between two faces (Experiment 1) or textures (two control experiments). All stimuli had the same amplitude spectrum and were presented at 11 phase noise levels, varying from 0% to 100% in 10% increments, using a linear phase interpolation technique. Single-trial ERP data from each subject were analysed using a multiple linear regression model.ResultsOur results show that sensitivity to phase noise in faces emerges progressively in a short time window between the P1 and the N170 ERP visual components. The sensitivity to phase noise starts at about 120–130 ms after stimulus onset and continues for another 25–40 ms. This result was robust both within and across subjects. A control experiment using pink noise textures, which had the same second-order statistics as the faces used in Experiment 1, demonstrated that the sensitivity to phase noise observed for faces cannot be explained by the presence of global image structure alone. A second control experiment used wavelet textures that were matched to the face stimuli in terms of second- and higher-order image statistics. Results from this experiment suggest that higher-order statistics of faces are necessary but not sufficient to obtain the sensitivity to phase noise function observed in response to faces.ConclusionOur results constitute the first quantitative assessment of the time course of phase information processing by the human visual brain. We interpret our results in a framework that focuses on image statistics and single-trial analyses.

A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-/spl mu/m CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate.